> Hi group, here's a question:
>
> Can I synthesise a component described in Verilog, obtain an EDIF, then
> write a VHDL wrapper around it so as to integrate it into a greater
> VHDL project.
>
> yours in ignorance,
>
> Robin
Reply by Antti●July 20, 20062006-07-20
Robin Bruce schrieb:
> Hi group, here's a question:
>
> Can I synthesise a component described in Verilog, obtain an EDIF, then
> write a VHDL wrapper around it so as to integrate it into a greater
> VHDL project.
>
> yours in ignorance,
>
> Robin
you should yes.
most of the tools allow any mix of verilog-vhdl, but you can also use
edif as interim format
antti
Reply by Robin Bruce●July 20, 20062006-07-20
Hi group, here's a question:
Can I synthesise a component described in Verilog, obtain an EDIF, then
write a VHDL wrapper around it so as to integrate it into a greater
VHDL project.
yours in ignorance,
Robin