> ok..ny idea why the logic gets trimmed out??

Usually this means that none of the outputs is used in the design. Could be
some mismatch in the component declaration maybe... It's hard to say without
seeing the design... Try a minimalist design including the core only and
nothing else...


/Mikhail

ok..ny idea why the logic gets trimmed out??
Vivek

MM wrote:
> "Vivek Menon" <vivek.menon79@gmail.com> wrote in message
> news:1154616408.500264.170760@i42g2000cwa.googlegroups.com...
> > Can you please elaborate?
>
> Xilinx protects its IP and will not release synthesizable HDL (or perhaps
> the source has never been HDL in the first place). Instead you get a netlist
> file, which you need to add to your project. If you create new source file
> in ISE with a wizard it's done for you automatically. Otherwise you need to
> make sure that the macro search path is set properly, so that ISE can find
> the netlist.
> 
> /Mikhail

"Vivek Menon" <vivek.menon79@gmail.com> wrote in message
news:1154616408.500264.170760@i42g2000cwa.googlegroups.com...
> Can you please elaborate?

Xilinx protects its IP and will not release synthesizable HDL (or perhaps
the source has never been HDL in the first place). Instead you get a netlist
file, which you need to add to your project. If you create new source file
in ISE with a wizard it's done for you automatically. Otherwise you need to
make sure that the macro search path is set properly, so that ISE can find
the netlist.

/Mikhail

> 1. First of all, the HDL generated file for FFT core 3.2 is not
> synthesizable.

It's not supposed to be. You need to use the netlist that coregen produces.


/Mikhail

Can you please elaborate?
MM wrote:
> > 1. First of all, the HDL generated file for FFT core 3.2 is not
> > synthesizable.
>
> It's not supposed to be. You need to use the netlist that coregen produces.
> 
> 
> /Mikhail

Also the synthesis report shows the following:
Reading core <fft_testv4_r22_flow_ctrl_1.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_2.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_3.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_4.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_5.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_6.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_7.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_8.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_9.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_10.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_11.ngc>.
Reading core <fft_testv4_r22_cnt_ctrl_12.ngc>.
Reading core <fft_testv4_cmpy_3_dsp48_13.ngc>.
Reading core <fft_testv4_cmpy_3_dsp48_14.ngc>.
Reading core <fft_testv4_cmpy_3_dsp48_15.ngc>.
Reading core <fft_testv4_cmpy_3_dsp48_16.ngc>.
Reading core <fft_testv4_cmpy_3_dsp48_17.ngc>.
Reading module "fifo_memory.ngo" ( "fifo_memory.ngo" unchanged since
last run )...
Reading core <fifo_memory_fifo_generator_v2_0_as_1.ngc>.
Loading core <upload_bus_mux> for timing and area information for
instance <upload_bus_mux>.
Loading core <fft_testv4_r22_flow_ctrl_1> for timing and area
information for instance <BU46>.

I think this implies that my core is only being read and not loaded. If
it's loaded for timing and area information, my core would work.

Thanks in advance for your valuable suggestions.
Vivek

Vivek Menon wrote:
> Hi all,
> I am using the FFT coregen block with pipelined streaming option in my
> design implementation on a Virtex-4 FPGA. I am having a lot of issues
> with the implementation and have shortlisted them below:
> 1. First of all, the HDL generated file for FFT core 3.2 is not
> synthesizable. Is there any way to synthesize this block. I am using
> Xilinx ISE 7.1.4i and latest IP update.
> 2. I went back and instantiated the FFT core 3.1 and tried to use that
> in my design. My PNR report states that the FFT logic is trimmed off. I
> am not able to understand the problem.
> 3. Also, how do I compile the wrapper file??
> Please let me know if you have come across this problem.
> Thanks,
> Vivek

Hi all,
I am using the FFT coregen block with pipelined streaming option in my
design implementation on a Virtex-4 FPGA. I am having a lot of issues
with the implementation and have shortlisted them below:
1. First of all, the HDL generated file for FFT core 3.2 is not
synthesizable. Is there any way to synthesize this block. I am using
Xilinx ISE 7.1.4i and latest IP update.
2. I went back and instantiated the FFT core 3.1 and tried to use that
in my design. My PNR report states that the FFT logic is trimmed off. I
am not able to understand the problem.
3. Also, how do I compile the wrapper file??
Please let me know if you have come across this problem.
Thanks,
Vivek