That problem is not solved yet. I did add one D flip-flop before RXD. I
copied parts UART code here. Please give me some comment. Is this
problem i put the wrong flip-flop.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- UART MODUEL : BAUD RATE 115200 BPS
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity UARTNOBUF is
PORT(
SYSCLK : IN std_logic; --100 MHz from DCM
RS232_CTS_OUT : OUT std_logic;
RS232_RTS_IN : IN std_logic;
RS232_RX_DATA : IN std_logic;
RS232_TX_DATA : OUT std_logic;
RESET : IN std_logic;
READ : IN std_logic;
WRITE : IN std_logic;
DATAIN : OUT std_logic_vector(7 downto 0);
DATAOUT : IN std_logic_vector(7 downto 0);
RXRDY : OUT std_logic;
TXRDY : OUT std_logic;
parityerr : OUT std_logic;
framingerr : OUT std_logic
); --detail comments about these port, refer to
wrlogic component.
end UARTNOBUF;
architecture Behavioral of UARTNOBUF is
SIGNAL CLKX16 : std_ulogic;
SIGNAL TX,RX : std_logic;
SIGNAL txhold,txreg : std_logic_vector(7 DOWNTO
0); -- not dataintmp
SIGNAL txtag1,txtag2,txparity,TXCLK,TXDONE,paritycycle,txdatardy :
std_logic; -- tag bits for detecting
SIGNAL rxhold,rxreg : std_logic_vector(7 DOWNTO 0);-- Holds received
data for read
SIGNAL rxparity,paritygen,
rxstop,rxclk,rxidle,rxdatardy : std_logic; -- Parity bit of received
data
SIGNAL div2, div27a, div27b, LUTOUT : std_logic;
-----------------------------------------------------
signal writeb,readb,txrdyb : std_logic;
-----------------------------------------------------
signal txclkb,rxclkb : std_logic;
begin
rxdinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rx,
C => SYSCLK,
CE => '1',
CLR => '0',
D => RS232_RX_DATA
);
txinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register
('0')
PORT MAP (
Q => RS232_TX_DATA,
C => SYSCLK,
CE => '1',
CLR => '0',
D =>tx
);
writebuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => writeb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => write -- Data input
);
readbuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => readb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => read -- Data input
);
RXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rxrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => rxdatardy -- Data input
);
TXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => txrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => txrdyb -- Data input
);
------------------------------------------------------------------------------------------
--**************************************** BAUDRATE GENERATOR
************************************************************
-- use shift register and LUT to do the clock divide
clkprescale1: SRL16E --divide the signal with 27-- 16+11
GENERIC MAP (INIT => X"0000")
PORT MAP (
Q => div27a,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1', --A = 1111, 16 bits
CE => '1',
CLK => SYSCLK,
D => div27b
);
clkprescale2: SRL16E --divide the signal with 27-- 16+11
GENERIC MAP (INIT => X"0001")
PORT MAP (
Q => div27b,
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '1', --A = 1010, 11 bits
CE => '1',
CLK => SYSCLK,
D => div27a
);
clkprescale3: SRL16E --divide the signal with 2
GENERIC MAP (INIT => X"0001")
PORT MAP (
Q => div2,
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0', --A = 0001, 2 bits
CE => div27b, --using div27 as the enable signal
CLK => SYSCLK,
D => div2
);
LUT2_inst : LUT2
generic map ( INIT => X"9")
port map (
O => LUTOUT, -- LUT general output
I0 => div27b, -- LUT input
I1 => div2 -- LUT input
);
clkdiv1: FDCE
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => CLKX16, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => LUTOUT-- Data input
);
--**************************************** TRANSMITTING
************************************************************
...............................................................