I'd recommend searching the Xilinx APP notes for DRAM controllers; you might 
get good hits just by searching for "DQS."  There's a bit of literature 
already there.


"Thomas" <"Thomas.10.Hinz"@spamgourmet.com> wrote in message 
news:4nvh7nFbvulcU1@news.dfncis.de...
> Hello,
> I've got a Xilinx Virtex 4 FPGA and would like to address the onboard 
> DDR-SDRAM.
> I've found out that I can instantiate special DDR-IO flip flops by hand 
> (and found an example in the ISE-Webpack documentation).
> But I'm still not sure how to address the DDR-SDRAM best, especially I 
> don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need a 
> sensitivity on both edges.
>
> Perhaps someone can even help me with a short example (VHDL preferred).
>
> Thanks in advance,
>
> Thomas 

Thomas wrote:
> Hello,
> I've got a Xilinx Virtex 4 FPGA and would like to address the onboard
> DDR-SDRAM.
> I've found out that I can instantiate special DDR-IO flip flops by hand
> (and found an example in the ISE-Webpack documentation).
> But I'm still not sure how to address the DDR-SDRAM best, especially I
> don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need
> a sensitivity on both edges.
> 
> Perhaps someone can even help me with a short example (VHDL preferred).

Did you ever work with FPGA and DDR before ?

From your post I'd recommend just take an existing DDR controller and
don't try to do one yourself. Even doing that is sometimes tricky ...


   Sylvain

Hello,
I've got a Xilinx Virtex 4 FPGA and would like to address the onboard 
DDR-SDRAM.
I've found out that I can instantiate special DDR-IO flip flops by hand 
(and found an example in the ISE-Webpack documentation).
But I'm still not sure how to address the DDR-SDRAM best, especially I 
don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need 
a sensitivity on both edges.

Perhaps someone can even help me with a short example (VHDL preferred).

Thanks in advance,

Thomas