Al:

I am also using an XUP (V2P) board and thought about what you are
proposing. How would I go about accessing the EDK DDR controller from
ISE without having to go through the PowerPC?
Basically, I want one RAM controller that I can access from EDK and
ISE.

Al wrote:
> I ran into this same dilema using a xilinx xup board.  If you have a
> DDR core you can integrate with ISE, I would recomend adding a couple
> GPIO IP blocks to your EDK design and then exporting to ISE so you can
> connect the DDR core and whatever logic you need to support it.
>
> akcooper8@gmail.com wrote:
> > I need help on how to use the EDK DDR memory controller in ISE to write
> > to/from ram and fpga directly.  I have implemented the FFT provided by
> > Xilinx Coregen but need a faster memory controller to streamline the
> > FFT process rather than the EDK-PowerPC DDR controller in C that is
> > provided. Any help is appreciated.
> > 
> > Thanks
> > 
> > Ashwin

I ran into this same dilema using a xilinx xup board.  If you have a
DDR core you can integrate with ISE, I would recomend adding a couple
GPIO IP blocks to your EDK design and then exporting to ISE so you can
connect the DDR core and whatever logic you need to support it.

akcooper8@gmail.com wrote:
> I need help on how to use the EDK DDR memory controller in ISE to write
> to/from ram and fpga directly.  I have implemented the FFT provided by
> Xilinx Coregen but need a faster memory controller to streamline the
> FFT process rather than the EDK-PowerPC DDR controller in C that is
> provided. Any help is appreciated.
> 
> Thanks
> 
> Ashwin

if you don't like PowerPC DDR controller generated by EDK, you have to
use MIG tool to generate DDR controller which can interface with the
rest of fpga.


akcooper8@gmail.com wrote:
> I need help on how to use the EDK DDR memory controller in ISE to write
> to/from ram and fpga directly.  I have implemented the FFT provided by
> Xilinx Coregen but need a faster memory controller to streamline the
> FFT process rather than the EDK-PowerPC DDR controller in C that is
> provided. Any help is appreciated.
> 
> Thanks
> 
> Ashwin

what chip are you using, consider using MIG tool from xilinx to
generate DDR controller which can communication with fpga directly.


akcooper8@gmail.com wrote:
> I need help on how to use the EDK DDR memory controller in ISE to write
> to/from ram and fpga directly.  I have implemented the FFT provided by
> Xilinx Coregen but need a faster memory controller to streamline the
> FFT process rather than the EDK-PowerPC DDR controller in C that is
> provided. Any help is appreciated.
> 
> Thanks
> 
> Ashwin

I need help on how to use the EDK DDR memory controller in ISE to write
to/from ram and fpga directly.  I have implemented the FFT provided by
Xilinx Coregen but need a faster memory controller to streamline the
FFT process rather than the EDK-PowerPC DDR controller in C that is
provided. Any help is appreciated.

Thanks

Ashwin