Reply by Mike Treseler October 30, 20062006-10-30
fl wrote:
> Hi, > I am learning VHDL from Mike's example Uart.vhd in ISE 8.2. For > behavioral simulation, I can run Modelsim smoothly.
> After I check the library work, I find the work.uart (for other than > behavioral simulation) does not have char_len_g anymore (only the > source, i.e. behavioral file has that generic definition). How to deal > with this?
Choose one. 1. Skip the post-route sim because it is not normally needed with a synchronous design. 2. Search and replace the _g identifiers with constants. 3. Open a case with Xilinx and ask them to fix whatever software generates test_uart.ndo 4. Write your own do script using vsim -G as shown in the reference testbench. -- Mike Treseler
Reply by fl October 27, 20062006-10-27
Hi,
I am learning VHDL from Mike's example Uart.vhd in ISE 8.2. For
behavioral simulation, I can run Modelsim smoothly. But for other
simulation, such as post-translate or post-route simulation, there are
the following warnings:

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do {test_uart.ndo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar  8
2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity uart
# -- Compiling architecture structure of uart
# Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar  8
2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package uart_pkg
# -- Compiling entity test_uart
# -- Compiling architecture sim of test_uart
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Loading entity uart
# ** Error: test_uart.vhd(110): (vcom-1136) Unknown identifier
"char_len_g".
# ** Error: test_uart.vhd(111): (vcom-1136) Unknown identifier
"tic_per_bit_g".
# ** Error: test_uart.vhd(407): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.
# Error in macro ./test_uart.ndo line 7
# C:/Modeltech_xe_starter/win32xoem/vcom failed.
#     while executing
# "vcom -explicit  -93 "test_uart.vhd""

After I check the library work, I find the work.uart (for other than
behavioral simulation) does not have char_len_g anymore (only the
source, i.e. behavioral file has that generic definition). How to deal
with this?


Thank you in advance.





>From test_uart.vhd:
begin -- architecture sim dut : entity work.uart generic map (char_len_g => tb_char_g, -- for vsim command line overload tic_per_bit_g => tb_tics_g)