Hi Mark,

  The vho file cannot contain both VHDL and Verilog. If it does it is a
bug. Can you email me the vho file that is causing the problem?

Subroto Datta,
Altera Corp.

On Nov 6, 9:46 pm, Mark McDougall <m...@vl.com.au> wrote:
> I'm having problems getting a simulation running. Here's the recipe...
>
> Quartus output VHO file - contains VHDL & Verilog components.
> Testbench components - VHDL & Verilog components.
>
> Note (and I *think* this is part of the problem) the VHO file contains a
> certain verilog modle, whilst the testbench also contains an instance of
> the same module, albeit with *different* parameter values.
>
> Attempting to start the simulation under ModelSim ('vsim') loads a bunch
> of structures from the library, and then halts with an error that just
> does *not* make any sense at all!
>
> The error is "irda_peripheral.v(155) The width (1) of VHDL port
> 'addr_cnt_out_2' does not match the width (5) of its Verilog connection
> (3rd connection)".
>
> This error occurs in the file that contains a 2nd instance of the
> verilog module, and the 3rd connection is indeed a vector whose width is
> specified with a parameter - which incidently differs from the value for
> the instance inside the VHO file.
>
> However:
>
> * addr_cnt_out is internal to the VHO and not connected to the instance
> in this file at all.
> * neither of the parameters specify a width of '1' for the vector.
>
> I suspect Modelsim is getting confused between the instance in the VHO
> file and the instance in irda_peripheral.v and is having trouble wiring
> up the ports?!?
>
> Anyone else had a similar experience?
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266

Paul Uiterlinden wrote:

> Have a look in the ModelSim User's Manual, in chapter 'Compiling
> Verilog Files'. There is a paragraph "Handling sub-modules with
> common names". It mentions the special meaning of the vsim option
> -L work:

Thanks, I'll check it out...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

> I'm having problems getting a simulation running. Here's the
> recipe...
> 
> Quartus output VHO file - contains VHDL & Verilog components.
> Testbench components - VHDL & Verilog components.
> 
> Note (and I *think* this is part of the problem) the VHO file
> contains a certain verilog modle, whilst the testbench also contains
> an instance of the same module, albeit with *different* parameter
> values.

Have a look in the ModelSim User's Manual, in chapter 'Compiling
Verilog Files'. There is a paragraph "Handling sub-modules with
common names". It mentions the special meaning of the vsim option
-L work:

"When you specify -L work first in the search library arguments you
are directing vsim to search for the instantiated module or UDP in
the library that contains the module that does the instantiation."

I'm not sure if this is exactly your problem.

-- 
Paul.
www.aimcom.nl
email address: switch x and s

I should probably also add, I have done successful post-PAR simulation
using VHO in the past on an ancestor of this very design! I didn't have
the verilog module that is seemingly causing my current problems...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mike Treseler wrote:

> Maybe you need a mixed language license from Mentor.

Already have, been running behavioural simulation with mixed-language
for yonks!

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:
> I'm having problems getting a simulation running. Here's the recipe...
> Quartus output VHO file - contains VHDL & Verilog components.
> Testbench components - VHDL & Verilog components.

Maybe you need a mixed language license from Mentor.

            -- Mike Treseler

I'm having problems getting a simulation running. Here's the recipe...

Quartus output VHO file - contains VHDL & Verilog components.
Testbench components - VHDL & Verilog components.

Note (and I *think* this is part of the problem) the VHO file contains a
certain verilog modle, whilst the testbench also contains an instance of
the same module, albeit with *different* parameter values.

Attempting to start the simulation under ModelSim ('vsim') loads a bunch
of structures from the library, and then halts with an error that just
does *not* make any sense at all!

The error is "irda_peripheral.v(155) The width (1) of VHDL port
'addr_cnt_out_2' does not match the width (5) of its Verilog connection
(3rd connection)".

This error occurs in the file that contains a 2nd instance of the
verilog module, and the 3rd connection is indeed a vector whose width is
specified with a parameter - which incidently differs from the value for
the instance inside the VHO file.

However:

* addr_cnt_out is internal to the VHO and not connected to the instance
in this file at all.
* neither of the parameters specify a width of '1' for the vector.

I suspect Modelsim is getting confused between the instance in the VHO
file and the instance in irda_peripheral.v and is having trouble wiring
up the ports?!?

Anyone else had a similar experience?

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266