Thanks, you are right. The example from the handbood is wrong.

Alan Nishioka a =E9crit :

> fl wrote:
> > Info: Selected device EP1C12Q240C6 for design "filtref"
> > Info: Fitter is performing a Standard Fit compilation using maximum
> > Fitter effort to optimize design performance
> > Error: Can't place node "clk" -- illegal location assignment PIN_G1
> > Error: Can't fit design in device
> > Error: Quartus II Fitter was unsuccessful. 2 errors, 0 warnings
>
> Well I haven't used Altera for a while, but it looks like an
> EP1C12Q240C6 is a 240 pin PQFP and doesn't have a pin G1.
>
> Either you need to change the part or you need to change the pin.
>=20
> Alan Nishioka

fl wrote:
> Info: Selected device EP1C12Q240C6 for design "filtref"
> Info: Fitter is performing a Standard Fit compilation using maximum
> Fitter effort to optimize design performance
> Error: Can't place node "clk" -- illegal location assignment PIN_G1
> Error: Can't fit design in device
> Error: Quartus II Fitter was unsuccessful. 2 errors, 0 warnings

Well I haven't used Altera for a while, but it looks like an
EP1C12Q240C6 is a 240 pin PQFP and doesn't have a pin G1.

Either you need to change the part or you need to change the pin.

Alan Nishioka

Hi,
I am new to tcl and quartus. When I try to follow the tcl example on
page 2-2, Quartus II handbook, vol. 2, I cannot pass the second step,
i.e. fitter, see the following. At the same directory, GUI does pass
well. I don't know what is wrong. Can you help me out? Thank you very
much.












# quartus_fit filtref --part=EP1C12Q240C6 --fmax=80MHz --tsu=8ns
Info:
*******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web
Edition
    Info: Copyright (C) 1991-2006 Altera Corporation. All rights
reserved.
    Info: Your use of Altera Corporation's design tools, logic
functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject

    Info: to the terms and conditions of the Altera Program License
    Info: Subscription Agreement, Altera MegaCore Function License
    Info: Agreement, or other applicable license agreement, including,
    Info: without limitation, that your use is for the sole purpose of
    Info: programming logic devices manufactured by Altera and sold by
    Info: Altera or its authorized distributors.  Please refer to the
    Info: applicable agreement for further details.
    Info: Processing started: Mon Nov 20 22:33:28 2006
Info: Command: quartus_fit filtref --part=EP1C12Q240C6 --fmax=80MHz
--tsu=8ns
Info: Selected device EP1C12Q240C6 for design "filtref"
Info: Fitter is performing a Standard Fit compilation using maximum
Fitter effort to optimize design performance
Error: Can't place node "clk" -- illegal location assignment PIN_G1
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 2 errors, 0 warnings
    Error: Processing ended: Mon Nov 20 22:33:30 2006
    Error: Elapsed time: 00:00:02
child process exited abnormally
#