karollo@o2.pl schrieb:
>> What signal you are talking about? Bidirectional ports? Did you ever
>> write to these signals?

> There are X(es) in the outputs. I'm sorry. I didn't describe it
> precisely. I've project in Altera and I want use it in actel (I don't
> use any altera library, it's pure vhdl)

I did not ask for the target technology but for the modelled hardware -
in other words: I was asking what you try to model.


> In Quartus d filp-flops, counters, registers etc. start from zeros,

Ok - a lot of FPGAs set Flipflops to a certain value after
configuration. I would not rely on it, because if you move to a
different target, it will be different. Use a reset.


> in
> model they are unkown at 0 ns and have x value through certain time.
> Do you know how change it in model to have known output values at 0
> time (forcing signals isn't the best idea).

Don't change the model - change your code! Include a reset and ask
yourself, why the signals switch to a certain value.

Without your code (a minimal example) we can only guess, what is happening.

Ralf

karollo@o2.pl wrote:
> > What signal you are talking about? Bidirectional ports? Did you ever
> > write to these signals?
>
> There are X(es) in the outputs. I'm sorry. I didn't describe it
> precisely. I've project in Altera and I want use it in actel (I don't
> use any altera library, it's pure vhdl)
> In Quartus d filp-flops, counters, registers etc. start from zeros, in
> model they are unkown at 0 ns and have x value through certain time.
> Do you know how change it in model to have known output values at 0
> time (forcing signals isn't the best idea).
>
> --
> Karl




I can think of three answers here:

1. You use the Quartus simulator. Whenever the output of quartus and
Modelsim differ, Modelsim is always right. So the correct answer _is_
'X', probably because you dont assert reset in the beginning of
simulation.


2. you actually mean post-synthesis simulation,

In pre-synthesis simulation, ('0' and 'X') yields '0', in
post-synthesis simulation on the other hand ('0' and 'X') yields 'X'.
Do a reset in the beginning of the simulation.

3.
In Altera you can decide the start value of memories and registers, in
Actel you cant do that. 
Do a reset in the beginning of the simulation.

> What signal you are talking about? Bidirectional ports? Did you ever
> write to these signals?

There are X(es) in the outputs. I'm sorry. I didn't describe it
precisely. I've project in Altera and I want use it in actel (I don't
use any altera library, it's pure vhdl)
In Quartus d filp-flops, counters, registers etc. start from zeros, in
model they are unkown at 0 ns and have x value through certain time.
Do you know how change it in model to have known output values at 0
time (forcing signals isn't the best idea).

-- 
Karl

karollo@o2.pl schrieb:

> I'm using Model for Actel. When performing pre-synthesis simulation in
> ModelSim, I observe 'unknown' signals in design.

Do you mean VHDL uninitialized 'U'?


What signal you are talking about? Bidirectional ports? Did you ever
write to these signals?

Ralf

I'm using Model for Actel. When performing pre-synthesis simulation in
ModelSim, I observe 'unknown' signals in design. However, these
signals are defined in simulation which I made in other simulator.
Thanks for help