Xilinx has these tools availalbe, called System Generator for DSP that
is a toolbox in Simulink environment.  JTAG cosim (for hardware
cosimulation) is one of the strongest reasons why customers use it.


jfh wrote:
> Hi,
>
> I imagine it would be pretty heavy in terms of communication but I have
> read and not investigated the fact that some hardware in the loop
> simulation was availbale when doing DSP functions with Simulink. I was
> wondering wether there wasn't a similar mechanism for other types of
> application.
>
> Best regards,
>
> JF Hasson
>
> Andy a =E9crit :
>
> > Co-simulation with real hardware would take a LOT of software work for
> > the API calls from the simulator to the hardware, and would require a
> > pretty good interface between the computer runninng the simulation and
> > the hardware.
> >
> > You  might try creating your testbenches such that they are
> > synthesizable, and load them into the chip too (assuming there's enough
> > room). You can't use assert statements or text io, but you could set
> > spare outputs that could be monitored with a scope or logic analyzer.
> >
> > With built-in wrap-around interfaces, the processor in the design could
> > run a lot of tests.
> >
> > Andy
> >
> >
> > jfh wrote:
> > > Hi,
> > >
> > > I am presently involved in a project dealing with a pretty large desi=
gn
> > > in a Stratix II GX chip with a Nios II processor. Is there anyway to
> > > perform hardware in the loop simulation where the Nios II would be
> > > running on a board while modelsim is simulating the design ? Does
> > > anyone have an advice as to how simulation times could be improved wh=
en
> > > involving Nios II processor ?
> > >=20
> > > Best regards,
> > >=20
> > > JF Hasson

Hi,

jfh schrieb:
> I am presently involved in a project dealing with a pretty large design
> in a Stratix II GX chip with a Nios II processor. Is there anyway to
> perform hardware in the loop simulation where the Nios II would be
> running on a board while modelsim is simulating the design ? Does
> anyone have an advice as to how simulation times could be improved when
> involving Nios II processor ?

Have a look at Semulator (www.ger-fae.com).
I have no practical experience with this system, but maybe you could
use it.

bye Thomas

Hi,

I imagine it would be pretty heavy in terms of communication but I have
read and not investigated the fact that some hardware in the loop
simulation was availbale when doing DSP functions with Simulink. I was
wondering wether there wasn't a similar mechanism for other types of
application.

Best regards,

JF Hasson

Andy a =E9crit :

> Co-simulation with real hardware would take a LOT of software work for
> the API calls from the simulator to the hardware, and would require a
> pretty good interface between the computer runninng the simulation and
> the hardware.
>
> You  might try creating your testbenches such that they are
> synthesizable, and load them into the chip too (assuming there's enough
> room). You can't use assert statements or text io, but you could set
> spare outputs that could be monitored with a scope or logic analyzer.
>
> With built-in wrap-around interfaces, the processor in the design could
> run a lot of tests.
>
> Andy
>
>
> jfh wrote:
> > Hi,
> >
> > I am presently involved in a project dealing with a pretty large design
> > in a Stratix II GX chip with a Nios II processor. Is there anyway to
> > perform hardware in the loop simulation where the Nios II would be
> > running on a board while modelsim is simulating the design ? Does
> > anyone have an advice as to how simulation times could be improved when
> > involving Nios II processor ?
> >=20
> > Best regards,
> >=20
> > JF Hasson

Co-simulation with real hardware would take a LOT of software work for
the API calls from the simulator to the hardware, and would require a
pretty good interface between the computer runninng the simulation and
the hardware.

You  might try creating your testbenches such that they are
synthesizable, and load them into the chip too (assuming there's enough
room). You can't use assert statements or text io, but you could set
spare outputs that could be monitored with a scope or logic analyzer.

With built-in wrap-around interfaces, the processor in the design could
run a lot of tests.

Andy


jfh wrote:
> Hi,
>
> I am presently involved in a project dealing with a pretty large design
> in a Stratix II GX chip with a Nios II processor. Is there anyway to
> perform hardware in the loop simulation where the Nios II would be
> running on a board while modelsim is simulating the design ? Does
> anyone have an advice as to how simulation times could be improved when
> involving Nios II processor ?
> 
> Best regards,
> 
> JF Hasson

Hi,

I am presently involved in a project dealing with a pretty large design
in a Stratix II GX chip with a Nios II processor. Is there anyway to
perform hardware in the loop simulation where the Nios II would be
running on a board while modelsim is simulating the design ? Does
anyone have an advice as to how simulation times could be improved when
involving Nios II processor ?

Best regards,

JF Hasson