>>
>> integer'image returns the textual representation of "int", but what is
>> wrong with simply writing "int"? Or I guess I should ask what the
>> difference between two is? (Is output of "int" type integer and output
>> of "integer'image" type char (or is it string of integers?)?)
>>
>I'm not sure what exactly you mean here or exactly what file format
>you're really trying to write. Try having the simulation write out the
>file and see what you get. If the file comes out in the format that
>you want, then you're done.
>
>KJ
>
With VHDL you can write binary files. This is the default. If you write to
a binary file, this will be in a machine-specific binary format that will
be difficult for a human to read, even with a hex-capable file editor.
If you need a file that humans can read, use text files via STD.TEXTIO
package procedures, as advised above.
Reply by KJ●December 11, 20062006-12-11
Vitaliy wrote:
> Thanks,
>
> When would one want to use std_logic_arith library over numeric_std?
'Never' would be the short answer to when you should use
std_logic_arith when writing new code.
If instead you're maintaining and supporting existing code that
somebody else wrote and they used std_logic_arith then in order to try
to avoid introducing new bugs caused by subtle differences between the
two libraries you might want to continue to have this legacy code use
std_logic_arith if you're making only otherwise minor changes.
>
> integer'image returns the textual representation of "int", but what is
> wrong with simply writing "int"? Or I guess I should ask what the
> difference between two is? (Is output of "int" type integer and output
> of "integer'image" type char (or is it string of integers?)?)
>
I'm not sure what exactly you mean here or exactly what file format
you're really trying to write. Try having the simulation write out the
file and see what you get. If the file comes out in the format that
you want, then you're done.
KJ
Reply by Vitaliy●December 11, 20062006-12-11
Thanks,
I realized from the error that each library has signed function and
that confuses the compiler, but didn't know std_logic_arith is not a
standard and I have to use numeric_std. When would one want to use
std_logic_arith library over numeric_std?
integer'image returns the textual representation of "int", but what is
wrong with simply writing "int"? Or I guess I should ask what the
difference between two is? (Is output of "int" type integer and output
of "integer'image" type char (or is it string of integers?)?)
Vitaliy
KJ wrote:
> "Vitaliy" <m.vitaliy@gmail.com> wrote in message
> news:1165779955.314942.70530@l12g2000cwl.googlegroups.com...
> > In to_integer(signed(My_slv)), does signed relate to integer or to
> > arithmetic (I think integer, but just checking)?
> 'signed' relates to how the std_logic_vector is supposed to be interpreted.
> All by itself std_logic_vectors have no implicit 'sign' bit or any sort of
> numerical interpretation so, for example, "10000000" could mean either 128
> (decimal) or a negative number or just a collection of 8 bits of 'stuff'.
> signed("10000000") means that the bit on the left is to be interpreted as a
> sign bit and the vector is a twos complement representation of a number,
> which means that in this case we're talking about a negative number, 8 bit
> numbers can represent anything from -128 to +127.
>
> There is also the function unsigned() which says that there is no sign bit
> in the std_logic_vector argument so unsigned("10000000") is a positive
> number, in this case 128. If you're only dealing with things that cannot be
> negative there is no value in the 'sign' bit, 8 bit numbers can represent
> anything from 0 to 255.
>
> To convert the std_logic_vector to an integer via the to_integer() function
> you need to supply it with an argument that has a specific interpretation
> which is what the signed() and unsigned() functions provide.
>
> > Because there are two libraries:
> > ieee.numeric_std.signed and ieee.std_logic_arith.signed
> Don't use std_logic_arith, it has problems and it is not a standard.
>
> > So, when I specify the complete name of the library (i.e
> > ieee.numeric_std.signed), the compiler is happy.
> Since both libraries have a 'signed' function and the compiler can't tell
> the difference between the two of them by their usage, specifying the full
> path name to the function that you want is the work around. Sometimes this
> is handy but in this particular instance you'd be better off getting rid of
> std_logic_arith.
>
> By the way, since the title of the thread is ''Writing output signals to
> text file (VHDL)" I'm guessing that you actually want to write out this
> integer as text in which case you'll probably be needing to convert that
> integer to a text string in order to write it to a text file. This can be
> done with
> integer'image(My_integer)
> or combining with the conversion of the std_logic_vector to an integer....
> integer'image(to_integer(signed(My_slv))
>
> KJ
Reply by KJ●December 11, 20062006-12-11
"Vitaliy" <m.vitaliy@gmail.com> wrote in message
news:1165779955.314942.70530@l12g2000cwl.googlegroups.com...
> In to_integer(signed(My_slv)), does signed relate to integer or to
> arithmetic (I think integer, but just checking)?
'signed' relates to how the std_logic_vector is supposed to be interpreted.
All by itself std_logic_vectors have no implicit 'sign' bit or any sort of
numerical interpretation so, for example, "10000000" could mean either 128
(decimal) or a negative number or just a collection of 8 bits of 'stuff'.
signed("10000000") means that the bit on the left is to be interpreted as a
sign bit and the vector is a twos complement representation of a number,
which means that in this case we're talking about a negative number, 8 bit
numbers can represent anything from -128 to +127.
There is also the function unsigned() which says that there is no sign bit
in the std_logic_vector argument so unsigned("10000000") is a positive
number, in this case 128. If you're only dealing with things that cannot be
negative there is no value in the 'sign' bit, 8 bit numbers can represent
anything from 0 to 255.
To convert the std_logic_vector to an integer via the to_integer() function
you need to supply it with an argument that has a specific interpretation
which is what the signed() and unsigned() functions provide.
> Because there are two libraries:
> ieee.numeric_std.signed and ieee.std_logic_arith.signed
Don't use std_logic_arith, it has problems and it is not a standard.
> So, when I specify the complete name of the library (i.e
> ieee.numeric_std.signed), the compiler is happy.
Since both libraries have a 'signed' function and the compiler can't tell
the difference between the two of them by their usage, specifying the full
path name to the function that you want is the work around. Sometimes this
is handy but in this particular instance you'd be better off getting rid of
std_logic_arith.
By the way, since the title of the thread is ''Writing output signals to
text file (VHDL)" I'm guessing that you actually want to write out this
integer as text in which case you'll probably be needing to convert that
integer to a text string in order to write it to a text file. This can be
done with
integer'image(My_integer)
or combining with the conversion of the std_logic_vector to an integer....
integer'image(to_integer(signed(My_slv))
KJ
Reply by Ray Andraka●December 10, 20062006-12-10
Vitaliy wrote:
> In to_integer(signed(My_slv)), does signed relate to integer or to
> arithmetic (I think integer, but just checking)? Because there are two
> libraries:
>
> ieee.numeric_std.signed and ieee.std_logic_arith.signed
>
> So, when I specify the complete name of the library (i.e
> ieee.numeric_std.signed), the compiler is happy.
>
>
> Vitaliy
>
> KJ wrote:
>
>>"Vitaliy" <m.vitaliy@gmail.com> wrote in message
>>news:1165773211.677889.327250@73g2000cwn.googlegroups.com...
>>
>>>The writing is working now (I shrinked the input file too much, so
>>>there was nothing to be processed. Still have question about converting
>>>two's complement to integer.
>>>
>>>
>>>>2) The output of the core is two's complement. Is there a standard
>>>>procedure in VHDL to transform the data from two's complement to
>>>>integer?
>>>>
>>
>>To convert a std_logic_vector (ex. My_slv) that is being interpreted as
>>'twos complement' to an integer use...
>>
>>to_integer(signed(My_slv))
>>
>>KJ
>
>
Don't use both numeric_std and std_logic_arith. They have different
definitions for the same function names. If you do use both, then you
have to specify which one each library call belongs to.
Reply by Vitaliy●December 10, 20062006-12-10
In to_integer(signed(My_slv)), does signed relate to integer or to
arithmetic (I think integer, but just checking)? Because there are two
libraries:
ieee.numeric_std.signed and ieee.std_logic_arith.signed
So, when I specify the complete name of the library (i.e
ieee.numeric_std.signed), the compiler is happy.
Vitaliy
KJ wrote:
> "Vitaliy" <m.vitaliy@gmail.com> wrote in message
> news:1165773211.677889.327250@73g2000cwn.googlegroups.com...
> > The writing is working now (I shrinked the input file too much, so
> > there was nothing to be processed. Still have question about converting
> > two's complement to integer.
> >
> >>
> >> 2) The output of the core is two's complement. Is there a standard
> >> procedure in VHDL to transform the data from two's complement to
> >> integer?
> >>
> To convert a std_logic_vector (ex. My_slv) that is being interpreted as
> 'twos complement' to an integer use...
>
> to_integer(signed(My_slv))
>
> KJ
Reply by Vitaliy●December 10, 20062006-12-10
I'm getting this error in ModelSim:
# ** Error: design_top_tb.vhd(165): (vcom-1137) Identifier 'signed' is
not visible. Making two objects with the name 'signed' directly
visible via use clauses results in a conflict; neither object is made
directly visible. (LRM Section 10.4)
Vitaliy
KJ wrote:
> "Vitaliy" <m.vitaliy@gmail.com> wrote in message
> news:1165773211.677889.327250@73g2000cwn.googlegroups.com...
> > The writing is working now (I shrinked the input file too much, so
> > there was nothing to be processed. Still have question about converting
> > two's complement to integer.
> >
> >>
> >> 2) The output of the core is two's complement. Is there a standard
> >> procedure in VHDL to transform the data from two's complement to
> >> integer?
> >>
> To convert a std_logic_vector (ex. My_slv) that is being interpreted as
> 'twos complement' to an integer use...
>
> to_integer(signed(My_slv))
>
> KJ
Reply by KJ●December 10, 20062006-12-10
"Vitaliy" <m.vitaliy@gmail.com> wrote in message
news:1165773211.677889.327250@73g2000cwn.googlegroups.com...
> The writing is working now (I shrinked the input file too much, so
> there was nothing to be processed. Still have question about converting
> two's complement to integer.
>
>>
>> 2) The output of the core is two's complement. Is there a standard
>> procedure in VHDL to transform the data from two's complement to
>> integer?
>>
To convert a std_logic_vector (ex. My_slv) that is being interpreted as
'twos complement' to an integer use...
to_integer(signed(My_slv))
KJ
Reply by Vitaliy●December 10, 20062006-12-10
The writing is working now (I shrinked the input file too much, so
there was nothing to be processed. Still have question about converting
two's complement to integer.
Vitaliy
Vitaliy wrote:
> Hello,
>
> I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The
> outputs of the core are xk_re and xn_re.
> 1) I am expanding Xilinx-provided test bench file. I am trying to write
> the outputs to .out file. Below are the lines of the code I'm using for
> that.
>
> if (done='1' and busy='1') then
> i1<=1;
> end if;
> while (busy='1' and i1=1) loop
> write(my_line, xk_re);
> writeline(my_output, my_line);
> wait until clk='1';
> end loop;
>
> Basically, I want to write new value each clock cycle. However, the
> above procedure prevents the output produced (meaning xk_re and xn_re
> stay at 0, however xk_index does incrementat each clock cycle after
> done bit is issued by the core.
> I have also tried the following just to see if writing anything (simple
> counter in this case) during the time the data is supposed to be
> produced will prevent the data to be output. And, inded, the data was
> not produce (xk_im and xk_re remained at zero).
>
> if (done='1' and busy='1') then
> i1<=1;
> end if;
> while (busy='1' and i1=1) loop
> write(my_line, i2);
> writeline(my_output, my_line);
> i2<=i2+1;
> wait until clk='1';
> end loop;
>
> Any suggestions?
>
> 2) The output of the core is two's complement. Is there a standard
> procedure in VHDL to transform the data from two's complement to
> integer?
>
>
>
> Thanks,
> Vitaliy
> Ryerson University
> ----------------------------------------------------
> -- Input 9.375 MHz (period - 106.67ns) signal.
> -- This should apper in bin 768
> -- Fs = 50 MHz (period - 20 ns)
> -- FFT Points = 4096
> -- Bin Size = 50 MHz / 4096 points = 12.207 kHz
> -- 9.375 MHz / 12.207 kHz = 768 Bin
> ----------------------------------------------------
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> use ieee.std_logic_arith.all;
> use ieee.numeric_std.all;
> use std.textio.all;
> use ieee.std_logic_textio.all;
>
> ENTITY design_top_tb IS
> END design_top_tb;
>
> ARCHITECTURE behavior OF design_top_tb IS
>
> constant CLOCK_PERIOD : time := 20 ns;
> constant HALF_CLOCK_PERIOD : time := CLOCK_PERIOD / 2;
>
> file DATA_FILE : text is in "Copy_of_sine_9_375mhz_1.dat";
>
> COMPONENT design_top
> PORT(
> xn_re : IN std_logic_vector(23 downto 0);
> xn_im : IN std_logic_vector(23 downto 0);
> start : IN std_logic;
> nfft : IN std_logic_vector(3 downto 0);
> nfft_we : IN std_logic;
> fwd_inv : IN std_logic;
> fwd_inv_we : IN std_logic;
> scale_sch : IN std_logic_vector(11 downto 0);
> scale_sch_we : IN std_logic;
> ce : IN std_logic;
> clk : IN std_logic;
> rst : IN std_logic;
> xk_re : OUT std_logic_vector(23 downto 0);
> xk_im : OUT std_logic_vector(23 downto 0);
> xn_index : OUT std_logic_vector(11 downto 0);
> xk_index : OUT std_logic_vector(11 downto 0);
> rfd : OUT std_logic;
> busy : OUT std_logic;
> dv : OUT std_logic;
> edone : OUT std_logic;
> done : OUT std_logic;
> ovflo : OUT std_logic;
> locked : OUT std_logic
> );
> END COMPONENT;
>
> SIGNAL i : integer;
> SIGNAL i1 : integer:=2; --used for writing
> SIGNAL i2 : integer:=1;
> SIGNAL xn_re : std_logic_vector(23 downto 0) :=
> "000000000000000000000000";
> SIGNAL xn_im : std_logic_vector(23 downto 0) :=
> "000000000000000000000000";
> SIGNAL start : std_logic := '0';
> SIGNAL nfft : std_logic_vector(3 downto 0) := "1100"; -- for 4096 pt
> fft
> SIGNAL nfft_we : std_logic := '0';
> SIGNAL fwd_inv : std_logic := '1'; -- FFT=1 IFFT=0
> SIGNAL fwd_inv_we : std_logic := '0';
> SIGNAL scale_sch : std_logic_vector(11 downto 0) := "000000000000";
> SIGNAL scale_sch_we : std_logic;
> SIGNAL ce : std_logic := '1'; -- FFT always enabled
> SIGNAL clk : std_logic := '0';
> SIGNAL rst : std_logic := '1'; -- Start with DCM in reset
> SIGNAL xk_re : std_logic_vector(23 downto 0);
> SIGNAL xk_im : std_logic_vector(23 downto 0);
> SIGNAL xn_index : std_logic_vector(11 downto 0);
> SIGNAL xk_index : std_logic_vector(11 downto 0);
> SIGNAL rfd : std_logic := '0';
> SIGNAL busy : std_logic := '0';
> SIGNAL dv : std_logic := '0';
> SIGNAL edone : std_logic := '0';
> SIGNAL done : std_logic := '0';
> SIGNAL ovflo : std_logic := '0';
> SIGNAL locked : std_logic := '0';
>
> BEGIN
>
> uut: design_top PORT MAP(
> xn_re => xn_re,
> xn_im => xn_im,
> start => start,
> nfft => nfft,
> nfft_we => nfft_we,
> fwd_inv => fwd_inv,
> fwd_inv_we => fwd_inv_we,
> scale_sch => scale_sch,
> scale_sch_we => scale_sch_we,
> ce => ce,
> clk => clk,
> rst => rst,
> xk_re => xk_re,
> xk_im => xk_im,
> xn_index => xn_index,
> xk_index => xk_index,
> rfd => rfd,
> busy => busy,
> dv => dv,
> edone => edone,
> done => done,
> ovflo => ovflo,
> locked => locked
> );
>
> -- Clock
> clock_proc : process
> begin
> wait for HALF_CLOCK_PERIOD;
> clk <= not clk;
> end process;
>
> control : process
> begin
> wait for (100 ns+(CLOCK_PERIOD)); --wait for
> GSR
> rst <= '0'; --release DCM
> reset
> wait until (locked = '1' and locked'event); --wait for
> DCM lock
> wait for ((HALF_CLOCK_PERIOD)+(CLOCK_PERIOD*2));
> nfft_we <= '1';
> fwd_inv_we <= '1';
> scale_sch <= "010101010101";
> scale_sch_we <= '1';
> wait for CLOCK_PERIOD;
> nfft_we <= '0';
> fwd_inv_we <= '0';
> scale_sch_we <= '0';
> wait for CLOCK_PERIOD;
> start <= '1'; --start
> loading and transform
> wait for (CLOCK_PERIOD*8192);
> wait; -- will wait forever
> end process;
>
>
> data_read : process
> variable input_line : line;
> variable input_data : integer;
> file my_output : TEXT open WRITE_MODE is "file_io.out";
> -- above declaration should be in architecture declarations for
> multiple
> variable my_line : LINE;
> variable my_output_line : LINE;
> begin
> i <= 0;
> xn_re <= "000000000000000000000000";
> xn_im <= "000000000000000000000000";
> wait for CLOCK_PERIOD; -- push data
> to negative edge transition
> while not endfile(DATA_FILE) loop
> readline(DATA_FILE, input_line);
> read(input_line, input_data);
> xn_re <= conv_std_logic_vector(input_data, 24);
> i <= i + 1; --line index that returns the line number of the
> input file
> wait for CLOCK_PERIOD;
> end loop;
>
> if (done='1' and busy='1') then
> i1<=1;
> -- if (i1=0) then
> -- i2<=1;
> end if;
> while (busy='1' and i1=1) loop
> write(my_line, xk_re);
> writeline(my_output, my_line);
> ---- i1 <= i1-1;
> wait until clk='1';
> end loop;
> -- if (i1=0) then
> -- i2<=1;
> -- end if;
> -- wait for CLOCK_PERIOD * 12500; --12500
> -- ASSERT (FALSE) REPORT
> -- "Simulation successful (not a failure). No problems detected."
> -- SEVERITY FAILURE;
> end process;
> ----
> END;
Reply by Vitaliy●December 10, 20062006-12-10
Hello,
I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The
outputs of the core are xk_re and xn_re.
1) I am expanding Xilinx-provided test bench file. I am trying to write
the outputs to .out file. Below are the lines of the code I'm using for
that.
if (done='1' and busy='1') then
i1<=1;
end if;
while (busy='1' and i1=1) loop
write(my_line, xk_re);
writeline(my_output, my_line);
wait until clk='1';
end loop;
Basically, I want to write new value each clock cycle. However, the
above procedure prevents the output produced (meaning xk_re and xn_re
stay at 0, however xk_index does incrementat each clock cycle after
done bit is issued by the core.
I have also tried the following just to see if writing anything (simple
counter in this case) during the time the data is supposed to be
produced will prevent the data to be output. And, inded, the data was
not produce (xk_im and xk_re remained at zero).
if (done='1' and busy='1') then
i1<=1;
end if;
while (busy='1' and i1=1) loop
write(my_line, i2);
writeline(my_output, my_line);
i2<=i2+1;
wait until clk='1';
end loop;
Any suggestions?
2) The output of the core is two's complement. Is there a standard
procedure in VHDL to transform the data from two's complement to
integer?
Thanks,
Vitaliy
Ryerson University
----------------------------------------------------
-- Input 9.375 MHz (period - 106.67ns) signal.
-- This should apper in bin 768
-- Fs = 50 MHz (period - 20 ns)
-- FFT Points = 4096
-- Bin Size = 50 MHz / 4096 points = 12.207 kHz
-- 9.375 MHz / 12.207 kHz = 768 Bin
----------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY design_top_tb IS
END design_top_tb;
ARCHITECTURE behavior OF design_top_tb IS
constant CLOCK_PERIOD : time := 20 ns;
constant HALF_CLOCK_PERIOD : time := CLOCK_PERIOD / 2;
file DATA_FILE : text is in "Copy_of_sine_9_375mhz_1.dat";
COMPONENT design_top
PORT(
xn_re : IN std_logic_vector(23 downto 0);
xn_im : IN std_logic_vector(23 downto 0);
start : IN std_logic;
nfft : IN std_logic_vector(3 downto 0);
nfft_we : IN std_logic;
fwd_inv : IN std_logic;
fwd_inv_we : IN std_logic;
scale_sch : IN std_logic_vector(11 downto 0);
scale_sch_we : IN std_logic;
ce : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
xk_re : OUT std_logic_vector(23 downto 0);
xk_im : OUT std_logic_vector(23 downto 0);
xn_index : OUT std_logic_vector(11 downto 0);
xk_index : OUT std_logic_vector(11 downto 0);
rfd : OUT std_logic;
busy : OUT std_logic;
dv : OUT std_logic;
edone : OUT std_logic;
done : OUT std_logic;
ovflo : OUT std_logic;
locked : OUT std_logic
);
END COMPONENT;
SIGNAL i : integer;
SIGNAL i1 : integer:=2; --used for writing
SIGNAL i2 : integer:=1;
SIGNAL xn_re : std_logic_vector(23 downto 0) :=
"000000000000000000000000";
SIGNAL xn_im : std_logic_vector(23 downto 0) :=
"000000000000000000000000";
SIGNAL start : std_logic := '0';
SIGNAL nfft : std_logic_vector(3 downto 0) := "1100"; -- for 4096 pt
fft
SIGNAL nfft_we : std_logic := '0';
SIGNAL fwd_inv : std_logic := '1'; -- FFT=1 IFFT=0
SIGNAL fwd_inv_we : std_logic := '0';
SIGNAL scale_sch : std_logic_vector(11 downto 0) := "000000000000";
SIGNAL scale_sch_we : std_logic;
SIGNAL ce : std_logic := '1'; -- FFT always enabled
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '1'; -- Start with DCM in reset
SIGNAL xk_re : std_logic_vector(23 downto 0);
SIGNAL xk_im : std_logic_vector(23 downto 0);
SIGNAL xn_index : std_logic_vector(11 downto 0);
SIGNAL xk_index : std_logic_vector(11 downto 0);
SIGNAL rfd : std_logic := '0';
SIGNAL busy : std_logic := '0';
SIGNAL dv : std_logic := '0';
SIGNAL edone : std_logic := '0';
SIGNAL done : std_logic := '0';
SIGNAL ovflo : std_logic := '0';
SIGNAL locked : std_logic := '0';
BEGIN
uut: design_top PORT MAP(
xn_re => xn_re,
xn_im => xn_im,
start => start,
nfft => nfft,
nfft_we => nfft_we,
fwd_inv => fwd_inv,
fwd_inv_we => fwd_inv_we,
scale_sch => scale_sch,
scale_sch_we => scale_sch_we,
ce => ce,
clk => clk,
rst => rst,
xk_re => xk_re,
xk_im => xk_im,
xn_index => xn_index,
xk_index => xk_index,
rfd => rfd,
busy => busy,
dv => dv,
edone => edone,
done => done,
ovflo => ovflo,
locked => locked
);
-- Clock
clock_proc : process
begin
wait for HALF_CLOCK_PERIOD;
clk <= not clk;
end process;
control : process
begin
wait for (100 ns+(CLOCK_PERIOD)); --wait for
GSR
rst <= '0'; --release DCM
reset
wait until (locked = '1' and locked'event); --wait for
DCM lock
wait for ((HALF_CLOCK_PERIOD)+(CLOCK_PERIOD*2));
nfft_we <= '1';
fwd_inv_we <= '1';
scale_sch <= "010101010101";
scale_sch_we <= '1';
wait for CLOCK_PERIOD;
nfft_we <= '0';
fwd_inv_we <= '0';
scale_sch_we <= '0';
wait for CLOCK_PERIOD;
start <= '1'; --start
loading and transform
wait for (CLOCK_PERIOD*8192);
wait; -- will wait forever
end process;
data_read : process
variable input_line : line;
variable input_data : integer;
file my_output : TEXT open WRITE_MODE is "file_io.out";
-- above declaration should be in architecture declarations for
multiple
variable my_line : LINE;
variable my_output_line : LINE;
begin
i <= 0;
xn_re <= "000000000000000000000000";
xn_im <= "000000000000000000000000";
wait for CLOCK_PERIOD; -- push data
to negative edge transition
while not endfile(DATA_FILE) loop
readline(DATA_FILE, input_line);
read(input_line, input_data);
xn_re <= conv_std_logic_vector(input_data, 24);
i <= i + 1; --line index that returns the line number of the
input file
wait for CLOCK_PERIOD;
end loop;
if (done='1' and busy='1') then
i1<=1;
-- if (i1=0) then
-- i2<=1;
end if;
while (busy='1' and i1=1) loop
write(my_line, xk_re);
writeline(my_output, my_line);
---- i1 <= i1-1;
wait until clk='1';
end loop;
-- if (i1=0) then
-- i2<=1;
-- end if;
-- wait for CLOCK_PERIOD * 12500; --12500
-- ASSERT (FALSE) REPORT
-- "Simulation successful (not a failure). No problems detected."
-- SEVERITY FAILURE;
end process;
----
END;