Thanks, all of your posts were very helpful.

David

David wrote:

> Does anyone know if it is possible to define the values in a lookup
> table using VHDL compatible with Xilinx tools?  If so, does anyone have
> an example?  
> 
> Thanks, 
> 
> David
> 

I'm not sure which you are asking for:  A generic look-up containing 
your data coded as RTL, or instantiating a LUT-4 primitive with your 
init data.

For the former:

type int_array is array(natural range <>) of integer;
constant lut_data: int_array(0 to 15):= (0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0);
signal lut_addr: unsigned(3 downto 0);
signal lut_out: unsigned(7 downto 0);
attribute syn_keep of lut_out: signal is true;
begin


LUT_out <= to_unsigned(lut_data(to_integer(lut_addr)));

will infer a LUT with a 4 bit address and an 8 bit output containing the 
data specified by the constant lut_data.  This of course can also be an 
array of std_logic_vectors or whatever.  The syn_keep will force it into 
a LUT-4 when it is synthesized (you may need also to put syn_keeps on 
the address in order to keep it from absorbing any combinatorial logic 
on the address lines).

David wrote:
> Does anyone know if it is possible to define the values in a lookup
> table using VHDL compatible with Xilinx tools?  If so, does anyone have
> an example?  
> 
> Thanks, 
> 
> David
> 

www.rockylogic.com/freebies.html#LUT

On 2006-12-20, David <dpmontminy@gmail.com> wrote:
> Does anyone know if it is possible to define the values in a lookup
> table using VHDL compatible with Xilinx tools?  If so, does anyone have
> an example?  

Yes it is possible.
The following URL will give some information for example:

http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=10068&BV_SessionID=@@@@0973742724.1166634752@@@@&BV_EngineID=cccdaddjimklkhecefeceihdffhdfkf.0

(Answer record 10068)

/Andreas

Does anyone know if it is possible to define the values in a lookup
table using VHDL compatible with Xilinx tools?  If so, does anyone have
an example?  

Thanks, 

David