Frank,
I did this for all my coregen components, but I did it all manually, not
through the xilinx gui. I have a folder for my custom IP cores called
"myProcessorIPLib" and under this directory I created
pcores -> CoregenLib -> hdl -> vhdl
this is the standard directory stucture that xilinx uses. You can but all
of your common VHDL files in the vhdl directory. In your pao file you will
need to add the vhdl files that you want to compile. so for example, if you
have a file called tmp.vhdl you will have something like this
lib CoregenLib tmp vhdl
You can change CoregenLib to whatever your peripheral name is, so it's
probably going to look like
lib myperipheral_v1_00_a tmp vhdl
Once you have modified you pao file, you can instantiate your vhdl file in
your user_logic.vhd file as you would with any other component
instantiation.
Harry
I've done this before, but I had to do it the manual way.way to do this is
to create a shared components directory. You will still need the directory
stucture
"Frank van Eijkelenburg" <someone@home.com.invalid> wrote in message
news:45d4cec3$0$738$5fc3050@dreader2.news.tiscali.nl...
> Hi,
>
> I have a small microblaze system with my own ipif peripheral. In this
> peripheral I want to use a vhdl block which is also used in another part
> of my project. Is this possible? Because when building the system, the edk
> looks in the pcores/<peripheral name>/hdl/vhdl directory for sources
> (where it doesn't find the shared vhdl part and I don't want to place the
> shared vhdl code in this directory!).
>
> TIA,
> Frank
Reply by Frank van Eijkelenburg●February 15, 20072007-02-15
Hi,
I have a small microblaze system with my own ipif peripheral. In this peripheral
I want to use a vhdl block which is also used in another part of my project. Is
this possible? Because when building the system, the edk looks in the
pcores/<peripheral name>/hdl/vhdl directory for sources (where it doesn't find
the shared vhdl part and I don't want to place the shared vhdl code in this
directory!).
TIA,
Frank