Sandip wrote:
> Hi,
> 
> I am working with Virtex-4. I have generated a VHDL code and need it
> to communicate it with Power PC and some other cores such as UART and
> I2C which sits on the OPB. I am willing to connect my IP core to this
> bus. can anyone help me how to do this??
> 
> Thanks and regards,
> Sandip
> 

You also need an plb to opb bridge (available within the edk).

Frank

On 1 Mar 2007 22:44:05 -0800, "Sandip" <sandip.gaikwad@gmail.com>
wrote:

>Hi,
>
>I am working with Virtex-4. I have generated a VHDL code and need it
>to communicate it with Power PC and some other cores such as UART and
>I2C which sits on the OPB. I am willing to connect my IP core to this
>bus. can anyone help me how to do this??
>


You may use the generic OPB_IPIF from Xilinx ( directly or using the
create/Import peroipherla wizzard), or you may implement your own OPB
interface by reading the OPB specification. The first way is faster to
develop, while the second may have faster throughput

Best regards,

Zara

Hi,

I am working with Virtex-4. I have generated a VHDL code and need it
to communicate it with Power PC and some other cores such as UART and
I2C which sits on the OPB. I am willing to connect my IP core to this
bus. can anyone help me how to do this??

Thanks and regards,
Sandip