Thank you for all your reply.

I saw on the document to use

bitgen -w -g USerID:<userID> -g StartupClk:JTAGClk my_design my_design

What I used is bitgen -w <-g StartupClk:JTAGClk> -f bitgen.ut system

I also changed the JTAG clock as 200Khz in the ChipScope setting, with
or without -g StartupClk:JTAGClk, but all are same:
"waiting for core to be armed".

Here are the commands I used after inserted the ILA core. system.ngo
is generated by chipscope.

 ngdbuild -p xc5vlx50ff676-1 -nt timestamp -bm system.bmm
system.ngo -uc system.ucf system.ngd

map -o system_map.ncd -w -pr b system.ngd system.pcf

par -w -ol std system_map.ncd system.ncd system.pcf

trce -e 3 -xml system.twx system.ncd system.pcf

bitgen -w <-g StartupClk:JTAGClk>  -f bitgen.ut system

Anything wrong here?

"Rebecca" <pang.dudu.pang@hotmail.com> wrote in message
news:1173995035.186185.243100@b75g2000hsg.googlegroups.com...
>
> But I noticed when I load the input netlist file which is targeting on
> virtex5, the inserter didn't recongnized it and I have to changed it
> manually from virtex4 to virtex5. If I don't change this setting, it
> can still generated the .ngo file. Is there any problem?
>

Which version of the tools are you using? There are a few answer records on
Xilinx site covering problems in using ChipScope with Virtex 5, e.g. the
following for 8.2:
http://tinyurl.com/2m6bxf

and this for 9.1:
http://tinyurl.com/28gdls

/Mikhail

Rebecca wrote:
> Hi, All
> 
> The ChipScope gave me the message "Waiting for core to be armed" while
> the program can run on the board at the same time. 

<snip>

I had this problem using the USB cable and having the JTAG clock set too 
high.  Try using a lower JTAG clock setting...

Rob

On Mar 15, 6:01 pm, "MM" <m...@yahoo.com> wrote:
> > Yes, thant is the button with the exclamation mark.
> > And I used chipscope inserter.
>
> Then it does sound like a clock problem...  Open the design in the FPGA
> editor and see if the clock really makes it to the core...
>
> /Mikhail

Hard to see in the editor.
But I noticed when I load the input netlist file which is targeting on
virtex5, the inserter didn't recongnized it and I have to changed it
manually from virtex4 to virtex5. If I don't change this setting, it
can still generated the .ngo file. Is there any problem?

"Rebecca" <pang.dudu.pang@hotmail.com> wrote in message 
news:1173990547.149492.274780@y80g2000hsf.googlegroups.com...
>
> I tried but nothing happened, it alway gave me that message.
>
That was the button with the exclamation mark, right?

Did you use Chipscope inserter to instantiate the core or did you do it 
manually through HDL? The reason I am asking is because it is much easier to 
connect something wrong if you do it yourself...

/Mikhail 

> Yes, thant is the button with the exclamation mark.
> And I used chipscope inserter.

Then it does sound like a clock problem...  Open the design in the FPGA 
editor and see if the clock really makes it to the core...

/Mikhail 

On Mar 15, 5:35 pm, "MM" <m...@yahoo.com> wrote:
> "Rebecca" <pang.dudu.p...@hotmail.com> wrote in message
>
> news:1173990547.149492.274780@y80g2000hsf.googlegroups.com...
>
> > I tried but nothing happened, it alway gave me that message.
>
> That was the button with the exclamation mark, right?
>
> Did you use Chipscope inserter to instantiate the core or did you do it
> manually through HDL? The reason I am asking is because it is much easier to
> connect something wrong if you do it yourself...
>
> /Mikhail


Yes, thant is the button with the exclamation mark.
And I used chipscope inserter.
Thanks

It probably has to do with your choice of trigger condition. Does anything 
happen when you click on Trigger Now button?

/Mikhail

On Mar 15, 5:20 pm, "MM" <m...@yahoo.com> wrote:
> It probably has to do with your choice of trigger condition. Does anything
> happen when you click on Trigger Now button?
>
> /Mikhail

I tried but nothing happened, it alway gave me that message.

Hi, All

The ChipScope gave me the message "Waiting for core to be armed" while
the program can run on the board at the same time. I have a small test
project which includes a MicroBlaze with a DCM, a RS232 interface and
other necessary components. The DCM divides the input clock from
100MHz to 50Mhz. An application prints out something through the RS232
will be shown on the hyperterminal. It works fine on the board even
after I insert the ILA core. But I just can't get any sample data.

It is said on Xilinx web that this is because of clock. So I tried to
connect the chipscope clock to different place, DCM feedback clock,
input clock after global buffer. And I also include a second DCM with
the exactly same configuration with the first DCM because I saw on the
group somebody pointed out that DCM can't be locked when connected to
both user logic and chipscope.  I used the second DCM just for the
Chipscope.  I can't connect the the sys_clk_pin to the chipscope clock
input direclty otherwise Xilinx will give me error because it is
connected directly to non-global buffer logic in the ILA core.

Can somebody give me any hint? I think my clock should works fine
because I can see messages print out at hyperterminal.

Thanks a lot,
Rebecca.