hi,
you can do a number of things.
use one of the synthesis templates provided with ISE from the EDIT menu.
That code is behavioral in nature so should be similar to what you write.
Also, you can set the option from the Synthesis - Process Properties under
 the HDL options tab, Where you can choose the RAM style as BLOCK (from the
menu)...
this should prevent XST from using slices to implement RAM.
Hope this helps.
Good luck !
Btw, which synthesizer are you using ?
Cheers,
Adarsh
----- Original Message ----- 
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Newsgroups: comp.arch.fpga
Sent: Friday, January 16, 2004 9:25 PM
Subject: Block RAM


Hello all,

I am working on FFT and instead of using Xilinx Block RAM, I write the
memory block using VHDL codes. However, after compiling and synthesizing, it
seems like they are occupying the Xilinx FPGA slices. Thus, it occupies a
lot of CLB/gates.

Is there any such away that the memory is written in our own vhdl code but
it occupies the memory allocation (Block RAM) in FPGA ?


Thanks.

Buzz

Hello all,

I am working on FFT and instead of using Xilinx Block RAM, I write the =
memory block using VHDL codes. However, after compiling and =
synthesizing, it seems like they are occupying the Xilinx FPGA slices. =
Thus, it occupies a lot of CLB/gates.

Is there any such away that the memory is written in our own vhdl code =
but it occupies the memory allocation (Block RAM) in FPGA ?


Thanks.

Buzz=20