<EvalXX@gmail.com> wrote in message 
news:1175195472.611147.280310@n59g2000hsh.googlegroups.com...
> On Mar 28, 6:55 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
>> <jid...@hotmail.com> wrote in message
>>
>> news:1175098335.158323.203250@n59g2000hsh.googlegroups.com...
>>
>> The newer Xilinx programming cables (Parallel Cable IV, Platform Cable 
>> USB)
>> use comparators rather than simple buffers to establish proper voltage
>
>
> Where can I get these kind of comparators? What about multiple
> voltages? Any sample circuits I can use as a reference?
>
> Thanks
> - E.

Almost any kind of comparators?
Take a look at the Platform Cable USB Product Specification

http://direct.xilinx.com/bvdocs/publications/ds300.pdf

pages 11-12 for an idea what Xilinx does to get the voltage compliance and 
well-defined threshold values.  If you substitute the 5V LPT buffers for the 
CPLD, you can pretty much cut & paste your way from a Parallel-III to a 
Parallel-IV style cable (though you'd still refer to it in SW as a 
Paralell-III).

I should reiterate that having your VCC act as both a VREF and source for a 
DC-DC converter is a solid way to design for the 5V LPT interface and the 
lower-voltage JTAG interface. 

On Mar 28, 6:55 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> <jid...@hotmail.com> wrote in message
>
> news:1175098335.158323.203250@n59g2000hsh.googlegroups.com...
>
> The newer Xilinx programming cables (Parallel Cable IV, Platform Cable USB)
> use comparators rather than simple buffers to establish proper voltage


Where can I get these kind of comparators? What about multiple
voltages? Any sample circuits I can use as a reference?

Thanks
- E.

On 29 Mrz., 18:53, Peter Wallace <p...@karpy.com> wrote:
> On Wed, 28 Mar 2007 10:12:15 -0700, jidan1 wrote:
> > Hi,
>
> > To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3
> > XCS400) at the same time, I decided as a programmer to use the Xilinx
> > Parallel Cable III. I implemented the programmer 100% the same as found
> > in Xilinx's website (
> >http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html).
> > The programmer worked, but not without problems. For programming the
> > Atmel uC I used AVRdude, and for the FPGA, ISE9.1i. The ribbon-cable
> > from the LPT port to Programmer was 20cm long and from the programmer to
> > the uC/FPGA board was not more than 10 cm. The problem related with this
> > programmer were verification errors, i.e the PC can't program or read
> > properly from the board. The interesting thing is how these verification
> > problem came up. In the morning when I turn the PC and Board on, these
> > verification errors are a lot. When the code that I want to download is
> > big, its impossible to program the FPGA/uC, for small codes it works but
> > after many tries. After 10 tries or so, the programming works  correct
> > and no verification errors no matter how many times I try to download
> > the code or how big the code is, and this without even touching a thing
> > on the hardware!!!
>
> > Since this problem applies to more than one board, I assume the problem
> > must lay on the programmer itself. My explanation is that maybe the
> > buffer IC's get hot or something...I really don't know. I want to know
> > if there is anyone who has had problems with this programmer cable.
>
> > Thank You,
> > JJ
>
> I have a simple upgrade to the parallel cable III that has Schmitt
> triggers on the clock, and a simple shunt regulator with an LED that
> limits internal VCC to about 4V, giving TTL compatible LPT interface even
> if used with 5V JTAG.
>
> It works reliably with 2.5V to 5V JTAG chips
>
> I have PCBs which I can send for free as long as its in the USA (1"x1"
> card in envelope) Requires SMT assy
>
> Peter Wallace

Thanks Peter, but if you can show us the schematics that will be more
than enough.

JJ

Peter Wallace <pcw@karpy.com> wrote:
...
>  
> I have a simple upgrade to the parallel cable III that has Schmitt
> triggers on the clock, and a simple shunt regulator with an LED that
> limits internal VCC to about 4V, giving TTL compatible LPT interface even
> if used with 5V JTAG.

> It works reliably with 2.5V to 5V JTAG chips

> I have PCBs which I can send for free as long as its in the USA (1"x1"
> card in envelope) Requires SMT assy
>  
A combination of LVC Single Gate Schmitt Trigger and the LVC1T45 level
translator also works fine 

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Wed, 28 Mar 2007 10:12:15 -0700, jidan1 wrote:

> Hi,
> 
> To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3
> XCS400) at the same time, I decided as a programmer to use the Xilinx
> Parallel Cable III. I implemented the programmer 100% the same as found
> in Xilinx's website (
> http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html).
> The programmer worked, but not without problems. For programming the
> Atmel uC I used AVRdude, and for the FPGA, ISE9.1i. The ribbon-cable
> from the LPT port to Programmer was 20cm long and from the programmer to
> the uC/FPGA board was not more than 10 cm. The problem related with this
> programmer were verification errors, i.e the PC can't program or read
> properly from the board. The interesting thing is how these verification
> problem came up. In the morning when I turn the PC and Board on, these
> verification errors are a lot. When the code that I want to download is
> big, its impossible to program the FPGA/uC, for small codes it works but
> after many tries. After 10 tries or so, the programming works  correct
> and no verification errors no matter how many times I try to download
> the code or how big the code is, and this without even touching a thing
> on the hardware!!!
> 
> Since this problem applies to more than one board, I assume the problem
> must lay on the programmer itself. My explanation is that maybe the
> buffer IC's get hot or something...I really don't know. I want to know
> if there is anyone who has had problems with this programmer cable.
> 
> 
> Thank You,
> JJ
 
I have a simple upgrade to the parallel cable III that has Schmitt
triggers on the clock, and a simple shunt regulator with an LED that
limits internal VCC to about 4V, giving TTL compatible LPT interface even
if used with 5V JTAG.

It works reliably with 2.5V to 5V JTAG chips

I have PCBs which I can send for free as long as its in the USA (1"x1"
card in envelope) Requires SMT assy
 

Peter Wallace

On 29 Mrz., 01:04, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:
> jid...@hotmail.com schrieb:
>
> > Since this problem applies to more than one board, I assume the
> > problem must lay on the programmer itself. My explanation is that
> > maybe the buffer IC's get hot or something...I really don't know.
> > I want to know if there is anyone who has had problems with this
> > programmer cable.
>
> As I posted before, there are many issues with parallel cable 3,
> especially
> in conjunction with old versions of impact. (The old software versions
> simultaneously turn of
> the output enable and change the data output value resulting in a race
> condition)
>
> The main issue is, that the parallel port has TTL logic levels that
> only have a guaranteed V_OH of
>  2V. But a 5V powered 74HC125 has a threshold voltage of 2.5V which
> might never be reached.
> A 3.3V powered 75HC125 still has a threshold of 1.65V. In that range
> the slope of a parallel port output
> can be very slow, but the 74HC is quite fast. As a result noise on the
> parallel port will amplify to
> many clock edges to TCK.
>
> You can solder 2k resistors between each buffers input and output pin.
> (0402 SMT fits perfectly)
> This creates a schmitt trigger with a large hysteresis which helps a
> lot.
>
> For building your own cable there are CMOS families that have
> thresholds of 1/3 VCC instead of
> 1/2 VCC.
> A 50mV hysteresis is not enough, so you need the positive feedback
> from output to input in all cases.
>
> Kolja Sulimma

Thanks for your detailed reply Kolja, it sounds logical to me. But
there is one thing still unexplained to me and that is although the
Parallel-III programmer doesn't work at the beginning, when it starts
to work after many tries, it continues to work for hours with no
problems.Why??? It seems to me it has something to do with the
temperature of the buffer IC's!

On 29 Mrz., 00:10, "John_H" <newsgr...@johnhandwork.com> wrote:
> <jid...@hotmail.com> wrote in message
>
> news:1175119186.275874.78300@e65g2000hsc.googlegroups.com...
>
>
>
> > Thanks for sharing the schematics!
>
> > Hmm...the TDO and voltage sense line are the exactly the same as
> > orginally posted by Xilinix. For the other JTAG lines (TMS, TCK, TDI),
> > two schmitt-triggers and a buffer were used to increase noise
> > immunity. Thats a little bit too many components for my taste, but
> > seems to be reliable.
>
> Seems to be reliable as in... you've already tried it and seen your troubles
> go away?
>
> Your problem may not be on the Schmidt trigger side of your buffers but in
> the interface between the PC and the programmer chips.
>
> Have you tried your existing programmer on a different PC to see if the
> behavior is identical or vastly different?
>
> You could modify the Parallel-III style design with comparators and a
> low-voltage DC-DC boost converter with fixed 5V output to power the
> LPT-compatible circuit with a variable logic level I/O to get closer to
> Parallel-IV performance with a Parallel-III interface.

I have tried Parallel-III cable with 2 PC's, and with both of them
this problem existed.

jidan1@hotmail.com schrieb:

> Since this problem applies to more than one board, I assume the
> problem must lay on the programmer itself. My explanation is that
> maybe the buffer IC's get hot or something...I really don't know.
> I want to know if there is anyone who has had problems with this
> programmer cable.

As I posted before, there are many issues with parallel cable 3,
especially
in conjunction with old versions of impact. (The old software versions
simultaneously turn of
the output enable and change the data output value resulting in a race
condition)

The main issue is, that the parallel port has TTL logic levels that
only have a guaranteed V_OH of
 2V. But a 5V powered 74HC125 has a threshold voltage of 2.5V which
might never be reached.
A 3.3V powered 75HC125 still has a threshold of 1.65V. In that range
the slope of a parallel port output
can be very slow, but the 74HC is quite fast. As a result noise on the
parallel port will amplify to
many clock edges to TCK.

You can solder 2k resistors between each buffers input and output pin.
(0402 SMT fits perfectly)
This creates a schmitt trigger with a large hysteresis which helps a
lot.

For building your own cable there are CMOS families that have
thresholds of 1/3 VCC instead of
1/2 VCC.
A 50mV hysteresis is not enough, so you need the positive feedback
from output to input in all cases.

Kolja Sulimma

<jidan1@hotmail.com> wrote in message 
news:1175119186.275874.78300@e65g2000hsc.googlegroups.com...
>
> Thanks for sharing the schematics!
>
> Hmm...the TDO and voltage sense line are the exactly the same as
> orginally posted by Xilinix. For the other JTAG lines (TMS, TCK, TDI),
> two schmitt-triggers and a buffer were used to increase noise
> immunity. Thats a little bit too many components for my taste, but
> seems to be reliable.

Seems to be reliable as in... you've already tried it and seen your troubles 
go away?

Your problem may not be on the Schmidt trigger side of your buffers but in 
the interface between the PC and the programmer chips.

Have you tried your existing programmer on a different PC to see if the 
behavior is identical or vastly different?

You could modify the Parallel-III style design with comparators and a 
low-voltage DC-DC boost converter with fixed 5V output to power the 
LPT-compatible circuit with a variable logic level I/O to get closer to 
Parallel-IV performance with a Parallel-III interface. 

On 28 Mrz., 23:44, Duane Clark <junkm...@junkmail.com> wrote:
> jid...@hotmail.com wrote:
> > On 28 Mrz., 22:49, Duane Clark <junkm...@junkmail.com> wrote:
> >> jid...@hotmail.com wrote:
>
> >>> ...or did you actually mean you used two inverted schitt-triggers
> >>> becuase you didn't have one non-inverted schmitt-trigger :)
> >> Yep, thats what I meant ;)
>
> > LOL...you might have not known this, but by using two schmitt-triggers
> > (rather than one) you have made the programmer more noise immune! Do
> > you still have the schematic for this circuit?
>
> I originally got the circuit from someone here in this group (sorry, I
> forgot who). Anyway, here is a 60KB pdf:
>
> http://www.leewardfpga.com/par_jtag.pdf
>
> As you can see, if I have room on my circuit board, I simply stick this
> circuit and a connector on the board, and run a plain parallel cable
> between the computer and the board.

Thanks for sharing the schematics!

Hmm...the TDO and voltage sense line are the exactly the same as
orginally posted by Xilinix. For the other JTAG lines (TMS, TCK, TDI),
two schmitt-triggers and a buffer were used to increase noise
immunity. Thats a little bit too many components for my taste, but
seems to be reliable.