On Apr 18, 2:27 pm, jetm...@hotmail.com wrote:
> Hi Farhan,
>
> Here's how I wired the wishbone ATA controller to the OPB IPIF. I
> hope it helps.
>
> --- OPB2IPIF
>
> signal sig_o2i_Clk_o : std_log=
ic; -- opb2ipif_0
> signal sig_o2i_Reset_o : std_log=
ic;
> signal sig_o2i_Freeze_o : std_log=
ic;
> signal sig_o2i_AddrValid_o : std_log=
ic;
> signal sig_o2i_Burst_o : std_log=
ic;
> signal sig_o2i_RNW_o : std_log=
ic;
> signal sig_o2i_CS_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_CE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_RdCE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_WrCE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_Ack_i : std_log=
ic;
> signal sig_o2i_Retry_i : std_log=
ic;
> signal sig_o2i_Error_i : std_log=
ic;
> signal sig_o2i_ToutSup_i : std_log=
ic;
> signal sig_o2i_PostedWrInh_i : std_log=
ic;
> signal sig_o2i_AddrAck_i : std_log=
ic;
>
> signal sig_o2i_Addr_o_xil : std_log=
ic_vector(0 to 31);
> signal sig_o2i_Data_o_xil : std_log=
ic_vector(0 to 31);
> signal sig_o2i_BE_o_xil : std_log=
ic_vector(0 to 3);
> signal sig_o2i_Data_i_xil : std_log=
ic_vector(0 to 31);
>
> signal sig_o2i_Addr_o : std_log=
ic_vector(31 downto 0);
> signal sig_o2i_Data_o : std_log=
ic_vector(31 downto 0);
> signal sig_o2i_BE_o : std_log=
ic_vector( 3 downto 0);
> signal sig_o2i_Data_i : std_log=
ic_vector(31 downto 0);
>
> --- WISHBONE bus
>
> signal sig_wb_data_o : std_log=
ic_vector (31 downto 0);
> signal sig_wb_data_i : std_log=
ic_vector (31 downto 0);
> -- signal sig_wb_addr_o : std_log=
ic_vector (31 downto 0);
> signal sig_wb_cyc_o : std_log=
ic;
> signal sig_wb_stb_o : std_log=
ic;
> signal sig_wb_sel_o : std_log=
ic_vector ( 3 downto 0);
> signal sig_wb_we_o : std_log=
ic;
> signal sig_wb_ack_i : std_log=
ic;
> signal sig_wb_err_i : std_log=
ic;
> signal sig_wb_rty_i : std_log=
ic;
>
> --- Components
>
> component edk
> port (
>
> ...
>
> o2i_Clk_o_pin :=
out std_logic; -- opb2ipif_0 (for ATAHOST)
> o2i_Reset_o_pin :=
out std_logic;
> o2i_Freeze_o_pin :=
out std_logic;
> o2i_Addr_o_pin :=
out std_logic_vector(0 to 31);
> o2i_AddrValid_o_pin :=
out std_logic;
> o2i_Data_o_pin :=
out std_logic_vector(0 to 31);
> o2i_BE_o_pin :=
out std_logic_vector(0 to 3);
> o2i_Burst_o_pin :=
out std_logic;
> o2i_RNW_o_pin :=
out std_logic;
> o2i_CS_o_pin :=
out std_logic_vector(0 to 0);
> o2i_CE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_RdCE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_WrCE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_Data_i_pin :=
in std_logic_vector(0 to 31);
> o2i_Ack_i_pin :=
in std_logic;
> o2i_Retry_i_pin :=
in std_logic;
> o2i_Error_i_pin :=
in std_logic;
> o2i_ToutSup_i_pin :=
in std_logic;
> o2i_PostedWrInh_i_pin :=
in std_logic;
> o2i_AddrAck_i_pin :=
in std_logic;
>
> ...
>
> );
> end component;
>
> ---------------------------------------------------------=
----------
> --- DISK =
---
> ---------------------------------------------------------=
----------
>
> --- signals
>
> signal sig_disk_irq : std_log=
ic; -- disk module requests
> INTERRUPT
> signal sig_disk_dma_req : std_log=
ic; -- disk module requests
> DMA
> signal sig_disk_dma_ack : std_log=
ic;
>
> --- external pin glue
>
> signal sig_disk_reset_n : std_log=
ic;
> signal sig_disk_dd_i : std_log=
ic_vector (15 downto 0);
> signal sig_disk_dd_o : std_log=
ic_vector (15 downto 0);
> signal sig_disk_dd_t : std_log=
ic;
> signal sig_disk_dd_oe : std_log=
ic;
> signal sig_disk_da : std_log=
ic_vector ( 2 downto 0);
> signal sig_disk_cs0_n : std_log=
ic;
> signal sig_disk_cs1_n : std_log=
ic;
> signal sig_disk_dior_n : std_log=
ic;
> signal sig_disk_diow_n : std_log=
ic;
> signal sig_disk_iordy : std_log=
ic;
> signal sig_disk_intrq : std_log=
ic;
> signal sig_disk_dmarq : std_log=
ic;
> signal sig_disk_dmack_n : std_log=
ic;
>
> signal sig_disk_dasp_n : std_log=
ic; -- not used
> signal sig_disk_pdiag_n : std_log=
ic; -- not used
>
> --- core glue
>
> signal sig_disk_da_u : unsigne=
d(2 downto 0);
>
> signal sig_wb_addr_disk_u : unsigne=
d(6 downto 2);
> signal sig_wb_cs_disk : std_log=
ic;
>
> --- OCIDEC3 core
>
> component atahost_top
>
> generic (
> ARST_LVL : std_log=
ic :=3D '0'; -- asynchronous reset level
>
> TWIDTH : natural=
:=3D 8; -- counter width
>
> -- PIO mode 0 settings (@100MHz clock)
> PIO_mode0_T1 : natural=
:=3D 6; -- 70ns
> PIO_mode0_T2 : natural=
:=3D 28; -- 290ns
> PIO_mode0_T4 : natural=
:=3D 2; -- 30ns
> PIO_mode0_Teoc : natural=
:=3D 23; -- 240ns =3D=3D> T0 - T1 - T2 =3D
> 600 - 70 - 290 =3D 240
>
> -- Multiword DMA mode 0 settings (@100MHz=
clock)
> DMA_mode0_Tm : natural=
:=3D 4; -- 50ns
> DMA_mode0_Td : natural=
:=3D 21; -- 215ns
> DMA_mode0_Teoc : natural=
:=3D 21 -- 215ns =3D=3D> T0 - Td - Tm =3D
> 480 - 50 - 215 =3D 215
> );
>
> port(
>
> -- WISHBONE SYSCON signals
>
> wb_clk_i : in s=
td_logic; -- master clock in
> arst_i : in s=
td_logic :=3D '1'; -- asynchronous active low reset
> wb_rst_i : in s=
td_logic :=3D '0'; -- synchronous active high
> reset
>
> -- WISHBONE SLAVE signals
>
> wb_cyc_i : in s=
td_logic; -- valid bus cycle input
> wb_stb_i : in s=
td_logic; -- strobe/core select input
> wb_ack_o : out s=
td_logic; -- strobe acknowledge output
> wb_rty_o : out s=
td_logic; -- retry output
> wb_err_o : out s=
td_logic; -- error output
> wb_adr_i : in u=
nsigned(6 downto 2); -- A6 =3D '1' ATA devices
> selected
> =
-- A5 =3D
> '1' CS1- asserted, '0' CS0- asserted
> =
-- A4..A2
> ATA address lines
> =
-- A6 =3D '0' ATA
> controller selected
> wb_dat_i : in s=
td_logic_vector(31 downto 0); -- Databus in
> wb_dat_o : out s=
td_logic_vector(31 downto 0); -- Databus out
> wb_sel_i : in s=
td_logic_vector(3 downto 0); -- Byte select
> signals
> wb_we_i : in s=
td_logic; -- Write enable input
> wb_inta_o : out s=
td_logic; -- interrupt request signal IDE0
>
> -- DMA engine signals
>
> DMA_req : out s=
td_logic; -- DMA request
> DMA_Ack : in s=
td_logic; -- DMA acknowledge
>
> -- ATA signals
>
> resetn_pad_o : out s=
td_logic;
> dd_pad_i : in s=
td_logic_vector(15 downto 0);
> dd_pad_o : out s=
td_logic_vector(15 downto 0);
> dd_padoe_o : out s=
td_logic;
> da_pad_o : out u=
nsigned(2 downto 0);
> cs0n_pad_o : out s=
td_logic;
> cs1n_pad_o : out s=
td_logic;
>
> diorn_pad_o : out s=
td_logic;
> diown_pad_o : out s=
td_logic;
> iordy_pad_i : in s=
td_logic;
> intrq_pad_i : in s=
td_logic;
>
> dmarq_pad_i : in s=
td_logic;
> dmackn_pad_o : out s=
td_logic;
>
> debug_pio_sample_indata : out s=
td_logic
> );
> end component;
>
> signal sig_pio_sample : std_log=
ic;
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- EDK - Embedded Submodule =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> edk_inst : edk
>
> port map (
>
> ...
>
> --- OPB2IPIF
>
> o2i_Clk_o_pin =
=3D> sig_o2i_Clk_o,
> o2i_Reset_o_pin =
=3D> sig_o2i_Reset_o,
> o2i_Freeze_o_pin =
=3D> sig_o2i_Freeze_o,
> o2i_Addr_o_pin =
=3D> sig_o2i_Addr_o_xil,
> o2i_AddrValid_o_pin =
=3D> sig_o2i_AddrValid_o,
> o2i_Data_o_pin =
=3D> sig_o2i_Data_o_xil,
> o2i_BE_o_pin =
=3D> sig_o2i_BE_o_xil,
> o2i_Burst_o_pin =
=3D> sig_o2i_Burst_o,
> o2i_RNW_o_pin =
=3D> sig_o2i_RNW_o,
> o2i_CS_o_pin =
=3D> sig_o2i_CS_o,
> o2i_CE_o_pin =
=3D> sig_o2i_CE_o,
> o2i_RdCE_o_pin =
=3D> sig_o2i_RdCE_o,
> o2i_WrCE_o_pin =
=3D> sig_o2i_WrCE_o,
> o2i_Data_i_pin =
=3D> sig_o2i_Data_i_xil,
> o2i_Ack_i_pin =
=3D> sig_o2i_Ack_i,
> o2i_Retry_i_pin =
=3D> sig_o2i_Retry_i,
> o2i_Error_i_pin =
=3D> sig_o2i_Error_i,
> o2i_ToutSup_i_pin =
=3D> sig_o2i_ToutSup_i,
> o2i_PostedWrInh_i_pin =
=3D> sig_o2i_PostedWrInh_i,
> o2i_AddrAck_i_pin =
=3D> sig_o2i_AddrAck_i,
>
> ...
>
> );
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- =
---
> --- OPB IPIF to WB =
---
> --- =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> --- Reverse stupid xilinx "big endian" addressing
>
> o2i_xil1 : for i in 0 to 31 generate
> sig_o2i_Data_i_xil (31-i) =
<=3D sig_o2i_Data_i (i);
> sig_o2i_Data_o (i) =
<=3D sig_o2i_Data_o_xil (31-i);
> sig_o2i_Addr_o (i) =
<=3D sig_o2i_Addr_o_xil (31-i);
> end generate;
>
> o2i_xil2 : for i in 0 to 3 generate
> sig_o2i_BE_o (i) =
<=3D sig_o2i_BE_o_xil (3-i);
> end generate;
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- =
---
> --- HARDDISK - OCIDEC3 from O=
penCores ---
> --- =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> sig_disk_dma_ack <=3D '0';
>
> --- OPB2IPIF -> ATAHOST WISHBONE glue
>
> sig_wb_cs_disk <=3D '1' when sig_o2i_CS_o(=
0)=3D'1' AND sig_o2i_Addr_o
> (15 downto 8) =3D x"00" else '0';
>
> sig_wb_addr_disk_u <=3D unsigned(sig_o2i_Addr_o(6 do=
wnto 2)); -- A6
> =3D '1' ATA devices selected
> =
-- A5 =3D '1' CS1- asserted, '0' CS0- =
asserted
> =
-- A4..A2 ATA address lines
> =
-- A6 =3D '0' ATA controller selected
>
> sig_wb_cyc_o <=3D sig_wb_cs_disk; =
-- valid bus cycle
> sig_wb_stb_o <=3D sig_wb_cs_disk; =
-- strobe/core select
> sig_wb_we_o <=3D NOT(sig_o2i_RNW_o); =
-- Write enable
> sig_wb_sel_o <=3D (others=3D>'1'); =
-- Byte select signals
>
> sig_wb_data_o <=3D sig_o2i_Data_o; =
-- Databus
>
> sig_o2i_Data_i <=3D sig_wb_data_i; =
-- Databus
>
> sig_o2i_Ack_i <=3D sig_wb_ack_i; =
-- strobe ack
> sig_o2i_Retry_i <=3D sig_wb_rty_i; =
-- retry
> sig_o2i_Error_i <=3D sig_wb_err_i; =
-- error
>
> sig_o2i_PostedWrInh_i <=3D '1';
> sig_o2i_ToutSup_i <=3D '1';
>
> --- ATAHOST -> I/O pads glue
>
> sig_disk_da <=3D std_logic_vector(sig_disk_da=
_u);
> sig_disk_dd_t <=3D NOT(sig_disk_dd_oe);
>
> --- Instantiate OCIDEC3 ATAHOST core
>
> disk_inst : atahost_top
>
> generic map (
> ARST_LVL =3D> '0',=
-- we're going to invert reset
>
> TWIDTH =3D> 8, =
-- counter width
>
> -- PIO mode 0 settings (@100MHz c=
lock)
>
> PIO_mode0_T1 =3D> 6, =
-- 70ns
> PIO_mode0_T2 =3D> 28, =
-- 290ns
> PIO_mode0_T4 =3D> 2, =
-- 30ns
> PIO_mode0_Teoc =3D> 23, =
-- 240ns =3D=3D> T0 - T1 - T2 =3D 600=
- 70 -
> 290 =3D 240
>
> -- Multiword DMA mode 0 settings =
(@100MHz clock)
>
> DMA_mode0_Tm =3D> 4, =
-- 50ns
> DMA_mode0_Td =3D> 21, =
-- 215ns
> DMA_mode0_Teoc =3D> 21 =
-- 215ns =3D=3D> T0 - Td - Tm =3D 480=
- 50 -
> 215 =3D 215
> )
>
> port map (
>
> -- WISHBONE SYSCON signals
>
> wb_clk_i =3D> CLK_=
OPB, -- master clock in
> arst_i =3D> NOT(=
RST), -- asynchronous active low reset
> wb_rst_i =3D> '0',=
-- synchronous active high reset
>
> -- WISHBONE SLAVE signals
>
> wb_cyc_i =3D> sig_=
wb_cyc_o, -- valid bus cycle input
> wb_stb_i =3D> sig_=
wb_stb_o, -- strobe/core select input
> wb_ack_o =3D> sig_=
wb_ack_i, -- strobe acknowledge output
> wb_rty_o =3D> sig_=
wb_rty_i, -- retry output
> wb_err_o =3D> sig_=
wb_err_i, -- error output
>
> wb_adr_i =3D> sig_=
wb_addr_disk_u, -- A6 =3D '1' ATA devices
> selected
> =
-- A5 =3D '1' CS1- asserted, '0' CS0- =
asserted
> =
-- A4..A2 ATA address lines
> =
-- A6 =3D '0' ATA controller selected
> wb_dat_i =3D> sig_=
wb_data_o, -- Databus in
> wb_dat_o =3D> sig_=
wb_data_i, -- Databus out
> wb_sel_i =3D> sig_=
wb_sel_o, -- Byte select signals
> wb_we_i =3D> sig_=
wb_we_o, -- Write enable input
>
> wb_inta_o =3D> sig_=
disk_irq, -- interrupt request signal IDE0
>
> -- DMA engine signals
>
> DMA_req =3D> sig_=
disk_dma_req, -- DMA request
> DMA_Ack =3D> sig_=
disk_dma_ack, -- DMA acknowledge
>
> -- ATA signals
>
> resetn_pad_o =3D> sig_=
disk_reset_n,
> dd_pad_i =3D> sig_=
disk_dd_i,
> dd_pad_o =3D> sig_=
disk_dd_o,
> dd_padoe_o =3D> sig_=
disk_dd_oe,
> da_pad_o =3D> sig_=
disk_da_u,
> cs0n_pad_o =3D> sig_=
disk_cs0_n,
> cs1n_pad_o =3D> sig_=
disk_cs1_n,
>
> diorn_pad_o =3D> sig_=
disk_dior_n,
> diown_pad_o =3D> sig_=
disk_diow_n,
> iordy_pad_i =3D> sig_=
disk_iordy,
> intrq_pad_i =3D> sig_=
disk_intrq,
>
> dmarq_pad_i =3D> sig_=
disk_dmarq,
> dmackn_pad_o =3D> sig_=
disk_dmack_n,
>
> debug_pio_sample_indata =3D> sig_=
pio_sample
> );
>
> --- Instantiate external pins
>
> disk_obuf_reset_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_reset_n,
> O =3D> FPGA=
_DD_RESET_N
> );
>
> disk_obuf_cs0_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_cs0_n,
> O =3D> FPGA=
_CS0_N
> );
>
> disk_obuf_cs1_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_cs1_n,
> O =3D> FPGA=
_CS1_N
> );
>
> disk_obuf_da0_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (0),
> O =3D> FPGA=
_DA0
> );
>
> disk_obuf_da1_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (1),
> O =3D> FPGA=
_DA1
> );
>
> disk_obuf_da2_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (2),
> O =3D> FPGA=
_DA2
> );
>
> disk_iobuf_dd : for i in 0 to 15 generate U1 : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dd_o (i),
> O =3D> sig_=
disk_dd_i (i),
> T =3D> sig_=
disk_dd_t,
> IO =3D> FPGA=
_DD_DD (i)
> );
>
> end generate;
>
> disk_obuf_dior_n : OBUF
>
> generic map (
> DRIVE =3D> 16,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dior_n,
> O =3D> FPGA=
_DIOR_HDMARDY_HSTB
> );
>
> disk_obuf_diow_n : OBUF
>
> generic map (
> DRIVE =3D> 16,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_diow_n,
> O =3D> FPGA=
_DIOW_STOP
> );
>
> disk_obuf_dmack_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dmack_n,
> O =3D> FPGA=
_DMACK_N
> );
>
> disk_iobuf_dmarq : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_dmarq,
> T =3D> '1',
> IO =3D> FPGA=
_DMARQ
> );
>
> disk_iobuf_intrq : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_intrq,
> T =3D> '1',
> IO =3D> FPGA=
_INTRQ
> );
>
> disk_iobuf_iordy : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_iordy,
> T =3D> '1',
> IO =3D> FPGA=
_IORDY_DDMARDY_DSTB
> );
>
> --- Pins outside of the scope of the core
>
> disk_obuf_csel : OBUF
>
> generic map (
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> FPGA=
_CSEL
> );
>
> --- Pins that are not used at all
>
> disk_ibuf_dasp_n : IBUF
>
> generic map (
> CAPACITANCE =3D> "LOW=
",
> IOSTANDARD =3D> "DEF=
AULT"
> )
>
> port map (
> I =3D> FPGA=
_DASP_N,
> O =3D> sig_=
disk_dasp_n
> );
>
> disk_ibuf_pdiag_n : IBUF
>
> generic map (
> CAPACITANCE =3D> "LOW=
",
> IOSTANDARD =3D> "DEF=
AULT"
> )
>
> port map (
> I =3D> FPGA=
_PDIAG_N,
> O =3D> sig_=
disk_pdiag_n
> );
>
> disk_obuf_sp1 : OBUF
>
> generic map (
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> DD_S=
P1
> );
>
> --- Pullup/pulldown resistors
>
> disk_pulldown_dd7 : PULLDOWN
> port map (
> O =3D> FPGA=
_DD_DD (7) -- ATA7 pg.38: 10k pulldown on DD7 to
> detect absence of a device
> );
>
> disk_pulldown_dmarq : PULLDOWN
> port map (
> O =3D> FPGA=
_DMARQ -- ATA7 pg.38: 5k6 pulldown
> );
>
> disk_pullup_iordy : PULLUP
> port map (
> O =3D> FPGA=
_IORDY_DDMARDY_DSTB -- ATA7 pg.38: 4k7 pullup
> );
>
> disk_pulldown_intrq : PULLDOWN
> port map (
> O =3D> FPGA=
_INTRQ -- ATA7 pg.38: 6k2 pulldown -> selects
> active-high
> );
Thanks Marc,
Well, I am a Verilog guy, will take some time to decipher VHDL code
into Verilog.
Will let you know in case I need more details.
Best Wishes,
Farhan