Peter,

Thank you for your explanation.

S. C.

On Apr 27, 12:12 pm, Peter Alfke <p...@xilinx.com> wrote:
> If you want to generate a precise average output frequency, you must
> NOT clear the accunulator.
> The unavoidable problem is then that the output periods vary, which is
> called jitter. The max jitter is (almost) one whole clock period.
> If you reset, you avoid the jitter, but you are not generating the
> frequency you intended to generate.
> Peter Alfke
>
> On Apr 27, 6:22 am, fp <fpga002...@yahoo.com> wrote:
>
>
>
> > Hi,
>
> > I am implementing a direct digital frequency synthesizer in FPGA.  It
> > follows the equation
>
> > Fo = N * Fs / (2^M)
>
> > The implementastion is done by an M-bit phase accumulator. My question
> > is: if 2^M cannot be divided by N, should the accumulator be cleared
> > to zero when wrapping around?
>
> > The VHDL code for automatical wrap-around is:
>
> > process(clk, reset)
> > begin
> >     if reset='1' then
> >         q<=(others=>'0');
> >     elsif rising_edge(clk) then
> >         q <= q + N;
> >     end if;
> > end process;
>
> > The VHDL code for clear-to-zero wrap-around is:
>
> > process(clk, reset)
> >     varaible:tmp: ...
> > begin
> >     tmp := q + N;
> >     if reset='1' then
> >         q<=(others=>'0');
> >     elsif rising_edge(clk) then
> >         if  (q > tmp) then  --reach 2^M-1 and wrap around
> >              q <= (others=>'0')
> >         else
> >              q<= tmp;
> >         end if;
> >     end if;
> > end process;
>
> > Which method is better ane why?  Thanks in advance.
>
> > S. C.- Hide quoted text -
>
> - Show quoted text -

If you want to generate a precise average output frequency, you must
NOT clear the accunulator.
The unavoidable problem is then that the output periods vary, which is
called jitter. The max jitter is (almost) one whole clock period.
If you reset, you avoid the jitter, but you are not generating the
frequency you intended to generate.
Peter Alfke

On Apr 27, 6:22 am, fp <fpga002...@yahoo.com> wrote:
> Hi,
>
> I am implementing a direct digital frequency synthesizer in FPGA.  It
> follows the equation
>
> Fo = N * Fs / (2^M)
>
> The implementastion is done by an M-bit phase accumulator. My question
> is: if 2^M cannot be divided by N, should the accumulator be cleared
> to zero when wrapping around?
>
> The VHDL code for automatical wrap-around is:
>
> process(clk, reset)
> begin
>     if reset='1' then
>         q<=(others=>'0');
>     elsif rising_edge(clk) then
>         q <= q + N;
>     end if;
> end process;
>
> The VHDL code for clear-to-zero wrap-around is:
>
> process(clk, reset)
>     varaible:tmp: ...
> begin
>     tmp := q + N;
>     if reset='1' then
>         q<=(others=>'0');
>     elsif rising_edge(clk) then
>         if  (q > tmp) then  --reach 2^M-1 and wrap around
>              q <= (others=>'0')
>         else
>              q<= tmp;
>         end if;
>     end if;
> end process;
>
> Which method is better ane why?  Thanks in advance.
>
> S. C.

Hi,

I am implementing a direct digital frequency synthesizer in FPGA.  It
follows the equation

Fo = N * Fs / (2^M)

The implementastion is done by an M-bit phase accumulator. My question
is: if 2^M cannot be divided by N, should the accumulator be cleared
to zero when wrapping around?

The VHDL code for automatical wrap-around is:

process(clk, reset)
begin
    if reset='1' then
        q<=(others=>'0');
    elsif rising_edge(clk) then
        q <= q + N;
    end if;
end process;

The VHDL code for clear-to-zero wrap-around is:

process(clk, reset)
    varaible:tmp: ...
begin
    tmp := q + N;
    if reset='1' then
        q<=(others=>'0');
    elsif rising_edge(clk) then
        if  (q > tmp) then  --reach 2^M-1 and wrap around
             q <= (others=>'0')
        else
             q<= tmp;
        end if;
    end if;
end process;

Which method is better ane why?  Thanks in advance.

S. C.