I understand that mig generated testbench is rather frustrating ;
but that being said, my question remains : is that code (35 files,
well documented, in verilog or vhdl) a good starting point for an
implementation of a ddr2 controller, or not ? Is there a DDR2 better
controller pattern somewhere ?

and another question, why memory manufacturers (micron) didn't provide
hdl wrappers for their components ?

On 2 Mai, 15:38, rpons...@gmail.com wrote:
> look at this link :
>
> Board Verification Test Specificationhttp://www.xilinx.com/products/boards/s3astarter/files/s3ask_test.zip
> (sdram directory)
>
> mig user guide, fig. 8-2 page 205http://www.xilinx.com/support/software/memory/protected/migug.pdf
>
> I am new to design, particularly to memory interface ; but in my
> opinion, testbench generated by coregen mig 1.7 (vhdl_xst_bl8) should
> be a good starting point : of course, you have to hack
> vhdl_xst_bl8_ddr2_test_bench_0.vhd according your needs ... or do I
> miss something ?
>
> It is true it lacks some example with a soft processor (but not
> necessarily  with microblaze / edk for those not using it ...)
>

well I happen to disagree. I have used MIG and the generated
testbench, and I can do it, if needed. But ONLY IF THAT IS LAST
option.

so far I was pretty calm about the DDR2 in Spartan-3A mainly as had
seen the onsite demos with rotating bitmaps on the VGA display.
I naturally assumed that those images come from DDR2 memory.

But after looking at the PicoBlaze stuff I now understand that the
VGA bitmap rotation demo was taking the Xilinx logo bitmap from
NOR Flash and not from DDR2 memory.

Hence there is no confirmation about the availability of MicroBlaze
system with DDR2 (as the VGA demo was not using EDK)

Oh, well maybe I am over-stressed, but I was hoping more to be honest.

So far I am not able to even generate ANY bitstream for Spartan-3A
that would get activated... only Xilinx supplied bitstreams start.
Any bitstreams generated make the INIT LED dimmed and do not start :(

Antti

look at this link :

Board Verification Test Specification
http://www.xilinx.com/products/boards/s3astarter/files/s3ask_test.zip
(sdram directory)

mig user guide, fig. 8-2 page 205
http://www.xilinx.com/support/software/memory/protected/migug.pdf

I am new to design, particularly to memory interface ; but in my
opinion, testbench generated by coregen mig 1.7 (vhdl_xst_bl8) should
be a good starting point : of course, you have to hack
vhdl_xst_bl8_ddr2_test_bench_0.vhd according your needs ... or do I
miss something ?

It is true it lacks some example with a soft processor (but not
necessarily  with microblaze / edk for those not using it ...)



On May 2, 12:23 pm, Antti <Antti.Luk...@xilant.com> wrote:
> On 2 Mai, 11:14, Jim Granville <no.s...@designtools.maps.co.nz> wrote:
>
>
>
> > Antti wrote:
> > > as of MicroBlaze reference designs - well USUALLY I would also just
> > > make a new one, but in this case th=EDs is the VERY FIRST xilinx low
> > > cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
> > > usually work. With DDR2 I have different experiences, its not always
> > > working, it causes timing issues also on Virtex-5. Spartan-3A is way
> > > slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
> > > core without the known working reference provided by Xilinx.
>
> > > This (and any other Microblaze ref design) is missing NOT AVAILABLE.
>
> > Sounds a reasonable expectation, no comment from anyone in Xilinx ?
>
> > It does suggest they have tried, and been unable to get this to
> > actual work themselves ?
>
> > Do they have ANY DDR2 templates that allow a bandwidth/memory test ?
>
> > -jg
>
> Hi Jim,
>
> well, the only available DDR2 thingie is the default MIG coregen
> autogenerated self checking test design, that should display fail-pass
> on single user LED.
>
> the only thing what this thing is good, is to deliver a result:
> "the DDR2 memory is not necessary fully dead"... for anything more
> reliable evaluation the LED status is not good IMHO.
>
> this design does really not allow any "bandwidth" evaluation, and its
> user interface is also awkward enough so that no-body wishes to mess
> around with unless really forced to do that. The MIG core can not be
> used without special statemachines in any design.
>
> As of do they have or not, well at X-Fest there was demo of some
> display things, rotate the knob and look Xilinx logo to rotate, I
> assume those demos use DDR2 memory (as it is the only external RAM on
> this board).
>
> So I assume Xilinx _HAS_ useable demos and reference designs
> demonstrating working DDR2 on Xilinx Spartan-3A kit.
> The only issue is that NONE of those demos is currently available :(
>
> Antti

On 2 Mai, 11:14, Jim Granville <no.s...@designtools.maps.co.nz> wrote:
> Antti wrote:
> > as of MicroBlaze reference designs - well USUALLY I would also just
> > make a new one, but in this case th=EDs is the VERY FIRST xilinx low
> > cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
> > usually work. With DDR2 I have different experiences, its not always
> > working, it causes timing issues also on Virtex-5. Spartan-3A is way
> > slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
> > core without the known working reference provided by Xilinx.
>
> > This (and any other Microblaze ref design) is missing NOT AVAILABLE.
>
> Sounds a reasonable expectation, no comment from anyone in Xilinx ?
>
> It does suggest they have tried, and been unable to get this to
> actual work themselves ?
>
> Do they have ANY DDR2 templates that allow a bandwidth/memory test ?
>
> -jg

Hi Jim,

well, the only available DDR2 thingie is the default MIG coregen
autogenerated self checking test design, that should display fail-pass
on single user LED.

the only thing what this thing is good, is to deliver a result:
"the DDR2 memory is not necessary fully dead"... for anything more
reliable evaluation the LED status is not good IMHO.

this design does really not allow any "bandwidth" evaluation, and its
user interface is also awkward enough so that no-body wishes to mess
around with unless really forced to do that. The MIG core can not be
used without special statemachines in any design.

As of do they have or not, well at X-Fest there was demo of some
display things, rotate the knob and look Xilinx logo to rotate, I
assume those demos use DDR2 memory (as it is the only external RAM on
this board).

So I assume Xilinx _HAS_ useable demos and reference designs
demonstrating working DDR2 on Xilinx Spartan-3A kit.
The only issue is that NONE of those demos is currently available :(

Antti

Antti wrote:

> as of MicroBlaze reference designs - well USUALLY I would also just
> make a new one, but in this case th�s is the VERY FIRST xilinx low
> cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
> usually work. With DDR2 I have different experiences, its not always
> working, it causes timing issues also on Virtex-5. Spartan-3A is way
> slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
> core without the known working reference provided by Xilinx.
> 
> This (and any other Microblaze ref design) is missing NOT AVAILABLE.

Sounds a reasonable expectation, no comment from anyone in Xilinx ?

It does suggest they have tried, and been unable to get this to
actual work themselves ?

Do they have ANY DDR2 templates that allow a bandwidth/memory test ?

-jg

On 2 Mai, 06:06, "Alex Gibson" <n...@alxx.org> wrote:
> <rpons...@gmail.com> wrote in message
>
> news:1177963764.891437.228400@c35g2000hsg.googlegroups.com...
>
> > there is one example in sdram directory of s3ask_test design (follow
> > 3A reference design in xilinx web site), but this is only an
> > implementation of the DDR2 testbench ; the one that is generated with
> > mig 1.7. (a led blink if memory fails)
>
> > In mig user guide ug086, there is a brief explanation of the design ;
> > and I am too new to design to use it without tb (i.e. read / write
> > example from fpga with picoblaze would be a must...) ; if you can
> > help, I will apperciate.
>
> > I got 3 starter kit 3A from avnet in less than 1,5 week
>
> Mine took about the same time from Avnet Australia.
>
> The canned examples are rather lacking at the moment.http://www.xilinx.co=
m/products/boards/s3astarter/reference_designs.htm
>
> A couple of microblaze examples would be nice :-)
>
> Shouldn't take to much time to port the 3e examples.
> Getting the time to even look at the board is the problem for me.http://w=
ww.xilinx.com/products/boards/s3estarter/reference_designs.htm
>
> Alex

Hi Alex,

sorry about my mis-understandable statement about board delivery - the
delivery from Avnet was real quick, but it was resent to me, and that
delivery delayed. I did not specify that. So please everyone - Avnet
can deliver quick, and it should also arrive quick.

as of MicroBlaze reference designs - well USUALLY I would also just
make a new one, but in this case th=EDs is the VERY FIRST xilinx low
cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
usually work. With DDR2 I have different experiences, its not always
working, it causes timing issues also on Virtex-5. Spartan-3A is way
slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
core without the known working reference provided by Xilinx.

This (and any other Microblaze ref design) is missing NOT AVAILABLE.

I have lots of 3rd party made Xilinx boards - now I made a decision to
primarly use Xilinx own boards, in the HOPE for better support.

And result? I have the fresh new Xilinx board, and not that the
support is bad, no its NON EXISTANT.

I do not want to run the "factory test bitstream", this should be done
at the assembly/test site at the board manufacturer.

I want some known WORKING DDR2 memory desing for Xilinx Spartan-3A
Board.
(MIG blinking LED doesnt really count as such)

Antti

<rponsard@gmail.com> wrote in message 
news:1177963764.891437.228400@c35g2000hsg.googlegroups.com...
> there is one example in sdram directory of s3ask_test design (follow
> 3A reference design in xilinx web site), but this is only an
> implementation of the DDR2 testbench ; the one that is generated with
> mig 1.7. (a led blink if memory fails)
>
>
> In mig user guide ug086, there is a brief explanation of the design ;
> and I am too new to design to use it without tb (i.e. read / write
> example from fpga with picoblaze would be a must...) ; if you can
> help, I will apperciate.
>
> I got 3 starter kit 3A from avnet in less than 1,5 week
>

Mine took about the same time from Avnet Australia.

The canned examples are rather lacking at the moment.
http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm

A couple of microblaze examples would be nice :-)

Shouldn't take to much time to port the 3e examples.
Getting the time to even look at the board is the problem for me.
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm


Alex 

On 30 Apr., 22:09, rpons...@gmail.com wrote:
> there is one example in sdram directory of s3ask_test design (follow
> 3A reference design in xilinx web site), but this is only an
> implementation of the DDR2 testbench ; the one that is generated with
> mig 1.7. (a led blink if memory fails)

hi thanks..
I looked at the website and from the descriptions did not identify any
designs for DDR2, i will look again.. but the MIG "led blink" is no
what I look for actually..

Antti

one more complaint...

I was really disappointed that the EDK evaluation software was not
bundled and shipped with 3A kits (it was in 3E)...

there is one example in sdram directory of s3ask_test design (follow
3A reference design in xilinx web site), but this is only an
implementation of the DDR2 testbench ; the one that is generated with
mig 1.7. (a led blink if memory fails)


In mig user guide ug086, there is a brief explanation of the design ;
and I am too new to design to use it without tb (i.e. read / write
example from fpga with picoblaze would be a must...) ; if you can
help, I will apperciate.

I got 3 starter kit 3A from avnet in less than 1,5 week



On Apr 30, 2:43 pm, Antti <Antti.Luk...@xilant.com> wrote:
> an unhappy owner of the fresh new Spartan-3A development kit from
> Xilinx:
>
> reason for unhappiness:
>
> 1) NO examples how to use DDR2 IP core with Spartan3A
> 2) NO EDK reference design for this board at all
> 3) NO EDK Board support package available
>
> Spartan 3A is only supported by EDK 9.1, but EDK 9.1 seems have bugs
> that force the need to run synthesis manually (automated build doesnt
> work)
>
> Should we now really wait EDK 9.1 SP2 ?
>
> My Spartan-3A kit was delayed at post for 30 days, so when i finally
> got it I was extremly happy!!!
>
> But it seems it arrived too early as Xilinx has not support for this
> board yet? :(
>
> Antti