On May 23, 2:48 pm, johnp <johnp3+nos...@probo.com> wrote:
> I'm having a problem with Xilinx Navigator "discovering" a Verilog
> design hierarchy.
>
> I've inherited some IP that requires that a Verilog `define be set to
> specify
> the modules to include into the design. However, when Navigator starts
> up
> and builds the design hierarchy, I see no way to tell it about global
> macros
> definitions.
>
> I can manually go in and add `define values in the files (yuck), but
> I'm hoping
> someone has already figured out how to get Navigator to do this.
>
> Verilog allows you to define a macro via the command line using
> +define and
> XST apparently also allows macros to be defined via the synthesis
> property
> "Verilog Macros". I've found no way to do something similar with
> Navigator.
>
> Has anyone else run into this and found a work around?
>
> Thanks!
>
> John Providenza

One way is to include a common file in each file that needs it.
The common file would set the defines.  This gives one a common point
of control.

-Newman