The flexibility in logic and routing causes FPGAs to have lower speed
and higher power consumption than ASICs of similar technology.
FPGAs make up (partially) for this by always being at the cutting edge
of technology. 130 nm and 9-layer metal in high-volume production since
2003, 90 nm in Spartan3 volume production now.  Most ASICs use older
technology, and any existing ASIC design is hardly ever ported to a
newer technology. And at over one million dollars per mask set (plus
verification and test development costs), the number of ASIC customers
becomes naturally limited. FPGA manufacturers can amortize these same
costs over hundreds and thousands of applications.

Peter Alfke
=========================================
paraag wrote:
> 
> Hi
> 
> How do i compare asic power/timing features for the same design with
> an FPGA having that same design....i mean what tecnology does xilinx
> use to fabricate their die ,
> 
> The Xpower readings from the ISE foundation gives an estimate of power
> , but i would like to know with which asic flow is this power
> comparable ultimately leading to a hybrid chip ( if it was possible)
> 
> thanks
> Paraag

Hi

How do i compare asic power/timing features for the same design with
an FPGA having that same design....i mean what tecnology does xilinx
use to fabricate their die ,

The Xpower readings from the ISE foundation gives an estimate of power
, but i would like to know with which asic flow is this power
comparable ultimately leading to a hybrid chip ( if it was possible)

thanks
Paraag