I think what you are looking for is a synchorniser. That is a pair of
flip-flops where the first flip-flop gets clocked with a certain
frequency f_a while the second flip-flop gets clocked with another
frequency f_b. Hope this answers your query.

regards,
nachiket.

> > 
> > Both the LUT and the register are usually part of a CLB's logic.
> 
> Ok thanks for the ideas. For the simple flip-flop, It would need to be
> clocked by two clock domains. Is it possible to do this in a Virtex
> FPGA?? and for the LUT alternative, i will try it soon.
> 
> Jac

> You could use a 1-input lookup-table...
> 
> http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0283_267.html#wp1001293
> 
> But this you'd have to instantiate, I don't know what code you'd use to 
> infer it.
> 
> As an alternative, you could use a simple flip-flop... those are usually 
> inferred for all signals assigned in a clocked process. Or you can 
> instantiate one:
> 
> http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0176_160.html#wp1000992
> 
> Both the LUT and the register are usually part of a CLB's logic.

Ok thanks for the ideas. For the simple flip-flop, It would need to be
clocked by two clock domains. Is it possible to do this in a Virtex
FPGA?? and for the LUT alternative, i will try it soon.

Jac

Jacques athow wrote:

> Is it possible to infer in vhdl, some kind of logic that has the same
> property as that of a virtex block ram, but being of size 1 bit (just
> using CLB logic) ??
You could use a 1-input lookup-table...

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0283_267.html#wp1001293

But this you'd have to instantiate, I don't know what code you'd use to 
infer it.

As an alternative, you could use a simple flip-flop... those are usually 
inferred for all signals assigned in a clocked process. Or you can 
instantiate one:

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0176_160.html#wp1000992

Both the LUT and the register are usually part of a CLB's logic.

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])

Is it possible to infer in vhdl, some kind of logic that has the same
property as that of a virtex block ram, but being of size 1 bit (just
using CLB logic) ??

Thanks for any ideas
jac