On 12 oct, 04:32, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

It will not help in your current situation, but I would recommend
Active-HDL for your future designs (not free unfortunately). What we
do is that we do the design in a graphical manner with boxes connected
to each other in a schematic editor. Then each box is a VHDL file or
another level of schematic. That way it us MUCH easier to understand
the design than to try to understand the VHDL netlist. Each schematic
is converted automatically to a VHDL file, so it's always possible to
go back to a simple VHDL netlist if desired.

Patrick

On Oct 12, 1:32 am, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

I'd like to mention Lattice HDL Explorer. As far as I understand it's
exactly the thing you're looking for. It's not exactly free, it's part
of Lattice tool ispLever. The tools aren't too expensive and also
you'll be able to get a 60 days free evaluation if you'd like, just
contact Lattice local person for this.

Hope this helps,
Alex Y.

Hi,

    There is a simple solution, just use the 'black_box' constraint
applied to your top lovel blocks, you can synthetize without needing
to provide the code of the components, this will create a schematic of
the top level, does it help?

csb

On 12 oct, 12:44, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi,
>
> Thanks for your answer.
>
> I saw the RTL viewer but you have to synthesis your design.
> My goal is to view a simple level of design without providing the source
> file of each sub component.
> Which can be quite long for complexe designs.
>
> St=E9phane.
>
> "csantos" <cayetanosan...@gmail.com> a =E9crit dans le message de news:
> 1192181411.264969.300...@q5g2000prf.googlegroups.com...
> Hi St=E9phane,
>
>     You can use ISE (or not!) from Xilinx, since release 8 you have
> the possibility to show the schematic equivalent of your hdl, try
> right mouse button over 'design tools' or similar, after synthesis
> using XST, then you can browse into the blocks, and so on. I guess
> that using symplify or other tools you have something equivalent.
>
> good luck
>
> csb
>
> On 12 oct, 10:32, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
> wrote:
>
> > Hi all,
>
> > Does anyone know a free/simple software that would use vhdl files to
> > produce
> > a graphical view ?
> > The goal is to have a easier and faster read of the architecture of a v=
hdl
> > file and its components.
>
> > Thanks.
>
> > St=E9phane.

"St&#4294967295;phane Julhes" <sjulhes@adeneo.adetelgroup.com> wrote:

>Hi all,
>
>Does anyone know a free/simple software that would use vhdl files to produce 
>a graphical view ?
>The goal is to have a easier and faster read of the architecture of a vhdl 
>file and its components.

doxygen?

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

On 10=D4=C212=C8=D5, =CF=C2=CE=E74=CA=B132=B7=D6, "St=A8=A6phane Julhes" <s=
jul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=A8=A6phane.

you can try FPGA Advantage, it's mentor product. I use this for
develop for years and it's very easy for generate graphic VHDL.

On Oct 12, 11:32 am, "St=E9phane Julhes"
<sjul...@adeneo.adetelgroup.com> wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

There are Advanced Dataflow Viewer in Aldec Active-HDL and Dataflow
Viewer in ModelSim. But they are not free. They are both pretty
similar, after compiling the design you can browse its graphical
representation consisting of architectures, processes, ports and
connections. You can also use Dataflow Viewer for debugging during
simulation.

Advanced Dataflow demo from Aldec:
http://www.aldec.com/products/active-hdl/multimediademo/movies/advanced_dat=
aflow/

St�phane Julhes wrote:

> I saw the RTL viewer but you have to synthesis your design.
> My goal is to view a simple level of design without providing the source 
> file of each sub component.

I use the quartus rtl viewer.
  example:
  http://home.comcast.net/~mike_treseler/uart.pdf

If I synthesize a structural entity with
null architectures, I get just the top
level block diagram.

        -- Mike Treseler

Hi,

Thanks for your answer.

I saw the RTL viewer but you have to synthesis your design.
My goal is to view a simple level of design without providing the source 
file of each sub component.
Which can be quite long for complexe designs.

St�phane.

"csantos" <cayetanosantos@gmail.com> a &#4294967295;crit dans le message de news: 
1192181411.264969.300860@q5g2000prf.googlegroups.com...
Hi St&#4294967295;phane,

    You can use ISE (or not!) from Xilinx, since release 8 you have
the possibility to show the schematic equivalent of your hdl, try
right mouse button over 'design tools' or similar, after synthesis
using XST, then you can browse into the blocks, and so on. I guess
that using symplify or other tools you have something equivalent.

good luck

csb

On 12 oct, 10:32, "St&#4294967295;phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to 
> produce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St&#4294967295;phane.

Hi St=E9phane,

    You can use ISE (or not!) from Xilinx, since release 8 you have
the possibility to show the schematic equivalent of your hdl, try
right mouse button over 'design tools' or similar, after synthesis
using XST, then you can browse into the blocks, and so on. I guess
that using symplify or other tools you have something equivalent.

good luck

csb

On 12 oct, 10:32, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

Hi all,

Does anyone know a free/simple software that would use vhdl files to produce 
a graphical view ?
The goal is to have a easier and faster read of the architecture of a vhdl 
file and its components.

Thanks.

St�phane.