"colin" <colin_toogood@yahoo.com> schrieb im Newsbeitrag
news:1193927393.785875.316600@22g2000hsm.googlegroups.com...
>
> Surely this is a simple bom cost option. If each fpga needs 4.1 Mbit
> you would need two 8MBit PROMs seperately or an 8 and a 1MBit if
> combining them.
So I'm fine with my solution if cost doesn't matter, right? :-) Technically
it is not wrong, I guess...
Reply by colin●November 1, 20072007-11-01
On 1 Nov, 12:23, "Toni Merwec" <mistertorp...@freenet.de> wrote:
> "Patrick Dubois" <prdub...@gmail.com> schrieb im Newsbeitragnews:1193673009.082475.114600@k35g2000prh.googlegroups.com...
>
>
>
> > The two proms can be considered as one big prom twice as large. No
> > prom is exclusively dedicated to one FPGA in particular. For example,
> > the bit file for FPGA #1 might take 2/3 of the first prom and the bit
> > file for FPGA #2 might be half in prom #1 and half in prom #2. This is
> > handled for you when you create your mcs files for the proms.
>
> Okay, thank you very much. But one more question: What about the DO pins
> from the PROMs to the FPGA? In the Platform Flash In-System Programmable
> Configuration PROMs data sheet ds123.pdf (page 18) it is recommended to tie
> the DO outputs of both PROMs together and connect the FPGAs in series. I
> don't see any reason to do it this way. What I would have done normally
> (without having read the user guide) is having the DO of one PROM connected
> to one FPGA (DIN) and the other DO of the second PROM to the the other DIN
> of the remaining FPGA. What is the reason not to do so, i.e. is there any
> reason? Any help is highly appreciated!
>
> Regards
>
> Toni
Surely this is a simple bom cost option. If each fpga needs 4.1 Mbit
you would need two 8MBit PROMs seperately or an 8 and a 1MBit if
combining them.
Reply by Toni Merwec●November 1, 20072007-11-01
"Patrick Dubois" <prdubois@gmail.com> schrieb im Newsbeitrag
news:1193673009.082475.114600@k35g2000prh.googlegroups.com...
>
> The two proms can be considered as one big prom twice as large. No
> prom is exclusively dedicated to one FPGA in particular. For example,
> the bit file for FPGA #1 might take 2/3 of the first prom and the bit
> file for FPGA #2 might be half in prom #1 and half in prom #2. This is
> handled for you when you create your mcs files for the proms.
>
Okay, thank you very much. But one more question: What about the DO pins
from the PROMs to the FPGA? In the Platform Flash In-System Programmable
Configuration PROMs data sheet ds123.pdf (page 18) it is recommended to tie
the DO outputs of both PROMs together and connect the FPGAs in series. I
don't see any reason to do it this way. What I would have done normally
(without having read the user guide) is having the DO of one PROM connected
to one FPGA (DIN) and the other DO of the second PROM to the the other DIN
of the remaining FPGA. What is the reason not to do so, i.e. is there any
reason? Any help is highly appreciated!
Regards
Toni
Reply by David Spencer●October 29, 20072007-10-29
"Toni Merwec" <mistertorpedo@freenet.de> wrote in message
news:4725fc31$0$16670$9b4e6d93@newsspool3.arcor-online.net...
> Hi there,
>
> currently I am designing an FPGA board, featuring two Xilinx Virtex-4
> FPGAs. It should be possible to program them with onboard Xilinx Platform
> FLASH PROMs as well as via JTAG with the IMPACT software. For ease of use
> and debugging all components should be part of one coherent JTAG chain.
>
> Now I'd like to know HOW to connect two FPGAs and two Platform FLASH
> devices in one JTAG chain so that each FPGA can be programmed through the
> associated FLASH? How is the identification done (i.e. which FLASH is
> associated with which FPGA?!)?
>
> Thanks alot in advance...
>
> Regards
>
> Toni
Since you want one Flash per FPGA, you just connect the Flashes to the FPGAs
as if there was only one of each. You can then connect the JTAG chain
through all four devices in whatever order you want.
Reply by Uwe Bonnes●October 29, 20072007-10-29
Toni Merwec <mistertorpedo@freenet.de> wrote:
> Hi there,
> currently I am designing an FPGA board, featuring two Xilinx
> Virtex-4 FPGAs. It should be possible to program them with
> onboard Xilinx Platform FLASH PROMs as well as via JTAG with
> the IMPACT software. For ease of use and debugging all
components should be part of one coherent JTAG chain.
>
> Now I'd like to know HOW to connect two FPGAs and two
> Platform FLASH devices in one JTAG chain so that each
> FPGA can be programmed through the associated FLASH?
> How is the identification done (i.e. which FLASH is
> associated with which FPGA?!)?
Argh: a crosspost to many groups!
What's wrong with Figure 8 of the DS123 datasheet?
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by Patrick Dubois●October 29, 20072007-10-29
On 29 oct, 11:28, "Toni Merwec" <mistertorp...@freenet.de> wrote:
> Hi there,
>
> currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs.
> It should be possible to program them with onboard Xilinx Platform FLASH
> PROMs as well as via JTAG with the IMPACT software. For ease of use and
> debugging all components should be part of one coherent JTAG chain.
>
> Now I'd like to know HOW to connect two FPGAs and two Platform FLASH devices
> in one JTAG chain so that each FPGA can be programmed through the associated
> FLASH? How is the identification done (i.e. which FLASH is associated with
> which FPGA?!)?
>
> Thanks alot in advance...
>
> Regards
>
> Toni
The two proms can be considered as one big prom twice as large. No
prom is exclusively dedicated to one FPGA in particular. For example,
the bit file for FPGA #1 might take 2/3 of the first prom and the bit
file for FPGA #2 might be half in prom #1 and half in prom #2. This is
handled for you when you create your mcs files for the proms.
For the hardware connections, refer to the platform flash guide, page
18
http://direct.xilinx.com/bvdocs/publications/ds123.pdf
Patrick
Reply by Toni Merwec●October 29, 20072007-10-29
Hi there,
currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs.
It should be possible to program them with onboard Xilinx Platform FLASH
PROMs as well as via JTAG with the IMPACT software. For ease of use and
debugging all components should be part of one coherent JTAG chain.
Now I'd like to know HOW to connect two FPGAs and two Platform FLASH devices
in one JTAG chain so that each FPGA can be programmed through the associated
FLASH? How is the identification done (i.e. which FLASH is associated with
which FPGA?!)?
Thanks alot in advance...
Regards
Toni