On 5 Nov, 22:00, Vince <claesvinc...@gmail.com> wrote:
> On 5 nov, 16:13, rouzbe...@actel.com wrote:
>
>
>
> > Hi Vince,
>
> > There is an example for the ProASIC3 board onActelwebpage with
> > complete design files and documentation.
> > But this design does not use the PLL.http://www.actel.com/products/hardware/devkits_boards/proasic3_starte...
>
> > Check that the POWERDOWN input signal for the PLL is connected
> > correctly.
> > By default this input is Active low and should therefore be connected
> > to '1'.
> > When generating the PLL macro you can see/change this configuration.
>
> > If this is not the problem let me know and I can send you an example.
>
> > BR
> > Rouzbeh
>
> Hi Rouzbeh,
>
> I just have problems with the PLL macro, I have developed some
> examples on this board already using CoreABC, UART, VHDL Project etc.
> so I know how to work with the board. But always when I use the STATIC
> PLL Macro it gives me problems... I can't get it running correctly.
> Can you send me an example (where I get a 10MHz and 40MHz clock out of
> the static pll macro? (I can't find a static pll example on theACTEL
> website)
>
> Thanks for your help, kind regards.
>
> Vince
Hi Vince,
Please also make sure that you have connected VCC/GND to the PLL/s.
"Instructions for PLL Activation on ProASIC3 Starter Kit Board
In order to use the PLLs on the ProASIC3 starter kit board, power must
be applied to their
respective analog supply rails. For the west side PLL, known as PLF,
the VCCPLF line must be
connected to VCC, which is held at 1.5 V. The same is true for VCCPLC
of the PLL on the east side,
known as PLC. In addition, the VCOMPLF and VCOMPLC lines must be
connected to ground. We
do not connect these voltages by default on the board for three
reasons:
1. The PLC analog voltage rails are not available on A3P devices, only
on A3PE in the PQ208
package. Only the west side PLL, namely PLF, is available on A3P
devices in PQ208. In A3P
devices, the pins are used as general I/Os. The same board is used for
A3PE and A3P devices.
2. We want to demonstrate the lowest possible power consumption for
the part. Perpetually
powering the PLL lines would not achieve that.
3. It is easy to connect the appropriate pins together when desired.
That is why we make the pins
available on the headers.
A variety of valid connections are possible. Two examples are as
follows:
1. For PLF, connect pin 27 (VCCPLF) to pin 36 (VCC), and pin 25
(VCOMPLF) to pin 17 (GND).
2. For PLC, (A3PE only) connect pin 131 (VCCPLC) to pin 142 (VCC), and
pin 133 (VCOMPLC)
to pin 141 (GND).
To facilitate end users, we will be supplying jumper wires with
selected production versions of the kit
to allow end users to quickly connect and disconnect these voltage
supply rails. If a user has lost the
jumper wires or has a production kit without jumper wires, it is a
simple matter of soldering short
insulated connecting wire to the appropriate header pins on the J14A
and J14C headers."
Thanks
Rouzbeh
Reply by Vince●November 5, 20072007-11-05
On 5 nov, 16:13, rouzbe...@actel.com wrote:
> Hi Vince,
>
> There is an example for the ProASIC3 board on Actel webpage with
> complete design files and documentation.
> But this design does not use the PLL.http://www.actel.com/products/hardware/devkits_boards/proasic3_starte...
>
> Check that the POWERDOWN input signal for the PLL is connected
> correctly.
> By default this input is Active low and should therefore be connected
> to '1'.
> When generating the PLL macro you can see/change this configuration.
>
> If this is not the problem let me know and I can send you an example.
>
> BR
> Rouzbeh
Hi Rouzbeh,
I just have problems with the PLL macro, I have developed some
examples on this board already using CoreABC, UART, VHDL Project etc.
so I know how to work with the board. But always when I use the STATIC
PLL Macro it gives me problems... I can't get it running correctly.
Can you send me an example (where I get a 10MHz and 40MHz clock out of
the static pll macro? (I can't find a static pll example on the ACTEL
website)
Thanks for your help, kind regards.
Vince
Reply by ●November 5, 20072007-11-05
Hi Vince,
There is an example for the ProASIC3 board on Actel webpage with
complete design files and documentation.
But this design does not use the PLL.
http://www.actel.com/products/hardware/devkits_boards/proasic3_starter.aspx
Check that the POWERDOWN input signal for the PLL is connected
correctly.
By default this input is Active low and should therefore be connected
to '1'.
When generating the PLL macro you can see/change this configuration.
If this is not the problem let me know and I can send you an example.
BR
Rouzbeh
Reply by ●November 4, 20072007-11-04
>I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3
>evaluation board, I try to use the Static PLL macro from the Libero
>IDE since in the documentation of ACTEL they tell us to use this
>macro's for best performance,... But I can't get this system working
>anyone has some experience with this Macro? (An example will be fine)
ACTEL don't give an example?
It doesn't compile?
It compiles but gives the wrong clock rates?
It compiles but doesn't work at all?
What exactly have you done?
Imagine you fix TVs. A customer walks in, leaves their TV on the
counter, says "Doesn't work" and leaves. What kind of starting point
is that?
The TV man can at least switch the set on and see what happens. We
can't even do that. How can you imagine that we know where to begin?
Reply by Vince●November 3, 20072007-11-03
Hi all,
I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3
evaluation board, I try to use the Static PLL macro from the Libero
IDE since in the documentation of ACTEL they tell us to use this
macro's for best performance,... But I can't get this system working
anyone has some experience with this Macro? (An example will be fine)
Kind regards and thanks for the help,
Vince