On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote:
> On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote:
>
>
>
>
>
> > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>
> > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> > > >> >> Anuja wrote:
> > > >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> > > >> >> > How do i convert this to vhdl? I have to use a concurrent
> > > statement
> > > >> as
>
> > > >> >> Q <= Q_int when rst = '0' else '0';
>
> > > >> >Hi,
>
> > > >> >I am having simulation problems with my code. I am trying to convert
> > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> > > >> >change at all. Please let me know what the problem could be.
>
> > > >> Remove the line:
>
> > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> > > >> after the BEGIN of the architecture.- Hide quoted text -
>
> > > >> - Show quoted text -
>
> > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> > > >"00";
>
> > > Sorry, my bad. I read your code too quickly, and thought you were
> > > assigning to Q in the clocked precess as well.
>
> > > Try:
> > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> > > Or better:
> > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> > > - Show quoted text -
>
> > neither one works. I am still having the same problem
>
> I'm not sure where you got the code, but it looks like it is a flop
> with a synchronous reset and enable, and then anding the output with
> reset after the register.
>
> I would convert it as follows to a standard asynchronous reset
> circuit. The only difference in behavior would be if rst is high for
> less than a clock cycle, but not while the clock is actually rising
> (in which case the original circuit output would be 0 while rst, but
> return to whatever q_int was afterwards, whereas the new circuit will
> stay at 0 until something is clocked into q).
>
> process (clk, rst) is
> begin
> if rst = '1' then
> q <= (others => '0');
> elsif rising_edge(clk) and (en = '1') then
> q <= d;
> end if;
> end process;
>
> Hints: you don't need to write "(1 downto 0)" when that is the entire
> range of the array/vector. In a clocked process, you also don't need
> to reassign q (or q_int) to itself when it needs to remain the same.
>
> and get rid of that concurrent statement (it is handled now by the
> async reset)
>
> Andy- Hide quoted text -
>
> - Show quoted text -
I FOUND THE SOLUTION. INSTEAD OF USING TEMPORARY SIGNAL Q_INT, I
DIRECTLY UPDATED THE VALUE OF OUTPUT Q. IT IS WORKING FINE NOW.
Andys tip of not reassigning signals to itself really helped.
Thanks everybody.
Reply by Anuja●December 7, 20072007-12-07
On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote:
> On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote:
>
>
>
>
>
> > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>
> > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> > > >> >> Anuja wrote:
> > > >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> > > >> >> > How do i convert this to vhdl? I have to use a concurrent
> > > statement
> > > >> as
>
> > > >> >> Q <= Q_int when rst = '0' else '0';
>
> > > >> >Hi,
>
> > > >> >I am having simulation problems with my code. I am trying to convert
> > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> > > >> >change at all. Please let me know what the problem could be.
>
> > > >> Remove the line:
>
> > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> > > >> after the BEGIN of the architecture.- Hide quoted text -
>
> > > >> - Show quoted text -
>
> > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> > > >"00";
>
> > > Sorry, my bad. I read your code too quickly, and thought you were
> > > assigning to Q in the clocked precess as well.
>
> > > Try:
> > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> > > Or better:
> > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> > > - Show quoted text -
>
> > neither one works. I am still having the same problem
>
> I'm not sure where you got the code, but it looks like it is a flop
> with a synchronous reset and enable, and then anding the output with
> reset after the register.
>
> I would convert it as follows to a standard asynchronous reset
> circuit. The only difference in behavior would be if rst is high for
> less than a clock cycle, but not while the clock is actually rising
> (in which case the original circuit output would be 0 while rst, but
> return to whatever q_int was afterwards, whereas the new circuit will
> stay at 0 until something is clocked into q).
>
> process (clk, rst) is
> begin
> if rst = '1' then
> q <= (others => '0');
> elsif rising_edge(clk) and (en = '1') then
> q <= d;
> end if;
> end process;
>
> Hints: you don't need to write "(1 downto 0)" when that is the entire
> range of the array/vector. In a clocked process, you also don't need
> to reassign q (or q_int) to itself when it needs to remain the same.
>
> and get rid of that concurrent statement (it is handled now by the
> async reset)
>
> Andy- Hide quoted text -
>
> - Show quoted text -
I tried the solution you gave me. I am still having the same problem,
Q or Q_int is still "00" at all time
Reply by Anuja●December 7, 20072007-12-07
On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote:
> On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote:
>
>
>
>
>
> > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>
> > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> > > >> >> Anuja wrote:
> > > >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> > > >> >> > How do i convert this to vhdl? I have to use a concurrent
> > > statement
> > > >> as
>
> > > >> >> Q <= Q_int when rst = '0' else '0';
>
> > > >> >Hi,
>
> > > >> >I am having simulation problems with my code. I am trying to convert
> > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> > > >> >change at all. Please let me know what the problem could be.
>
> > > >> Remove the line:
>
> > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> > > >> after the BEGIN of the architecture.- Hide quoted text -
>
> > > >> - Show quoted text -
>
> > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> > > >"00";
>
> > > Sorry, my bad. I read your code too quickly, and thought you were
> > > assigning to Q in the clocked precess as well.
>
> > > Try:
> > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> > > Or better:
> > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> > > - Show quoted text -
>
> > neither one works. I am still having the same problem
>
> I'm not sure where you got the code, but it looks like it is a flop
> with a synchronous reset and enable, and then anding the output with
> reset after the register.
>
> I would convert it as follows to a standard asynchronous reset
> circuit. The only difference in behavior would be if rst is high for
> less than a clock cycle, but not while the clock is actually rising
> (in which case the original circuit output would be 0 while rst, but
> return to whatever q_int was afterwards, whereas the new circuit will
> stay at 0 until something is clocked into q).
>
> process (clk, rst) is
> begin
> if rst = '1' then
> q <= (others => '0');
> elsif rising_edge(clk) and (en = '1') then
> q <= d;
> end if;
> end process;
>
> Hints: you don't need to write "(1 downto 0)" when that is the entire
> range of the array/vector. In a clocked process, you also don't need
> to reassign q (or q_int) to itself when it needs to remain the same.
>
> and get rid of that concurrent statement (it is handled now by the
> async reset)
>
> Andy- Hide quoted text -
>
> - Show quoted text -
I cannot change the reset to ssynchronous. My employer wants it to be
synchronous.
The wait statement did not help. I have clk_temp <= not clk_temp after
5 ns; So, the clock is definately moving forward.
_
Reply by Andy●December 7, 20072007-12-07
On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote:
> On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>
>
>
> > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> > >> >> Anuja wrote:
> > >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> > >> >> > How do i convert this to vhdl? I have to use a concurrent
> > statement
> > >> as
>
> > >> >> Q <= Q_int when rst = '0' else '0';
>
> > >> >Hi,
>
> > >> >I am having simulation problems with my code. I am trying to convert
> > >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> > >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> > >> >change at all. Please let me know what the problem could be.
>
> > >> Remove the line:
>
> > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> > >> after the BEGIN of the architecture.- Hide quoted text -
>
> > >> - Show quoted text -
>
> > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> > >"00";
>
> > Sorry, my bad. I read your code too quickly, and thought you were
> > assigning to Q in the clocked precess as well.
>
> > Try:
> > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> > Or better:
> > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> > - Show quoted text -
>
> neither one works. I am still having the same problem
I'm not sure where you got the code, but it looks like it is a flop
with a synchronous reset and enable, and then anding the output with
reset after the register.
I would convert it as follows to a standard asynchronous reset
circuit. The only difference in behavior would be if rst is high for
less than a clock cycle, but not while the clock is actually rising
(in which case the original circuit output would be 0 while rst, but
return to whatever q_int was afterwards, whereas the new circuit will
stay at 0 until something is clocked into q).
process (clk, rst) is
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) and (en = '1') then
q <= d;
end if;
end process;
Hints: you don't need to write "(1 downto 0)" when that is the entire
range of the array/vector. In a clocked process, you also don't need
to reassign q (or q_int) to itself when it needs to remain the same.
and get rid of that concurrent statement (it is handled now by the
async reset)
Andy
Reply by Anuja●December 7, 20072007-12-07
On Dec 7, 9:44 am, Dave <dhsch...@gmail.com> wrote:
> On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote:
>
> > Hello
>
> > I am trying to convert the following code to vhdl
>
> > assign Q = (rst==0)?Q_int:1'do;
>
> > How do i convert this to vhdl? I have to use a concurrent statement as
> > this statement is not in the always block hence concurrent. I cannot
> > use an if then else statement as it is sequential.
>
> > Please help
>
> Could there be an issue with not having a "wait" at the bottom of your
> testbench process? Maybe that process is executing every delta cycle,
> with time never moving forward.
It maybe possible. Let me check on this and see what happens.
Reply by Dave●December 7, 20072007-12-07
On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote:
> Hello
>
> I am trying to convert the following code to vhdl
>
> assign Q = (rst==0)?Q_int:1'do;
>
> How do i convert this to vhdl? I have to use a concurrent statement as
> this statement is not in the always block hence concurrent. I cannot
> use an if then else statement as it is sequential.
>
> Please help
Could there be an issue with not having a "wait" at the bottom of your
testbench process? Maybe that process is executing every delta cycle,
with time never moving forward.
Reply by Anuja●December 7, 20072007-12-07
On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> >> >> Anuja wrote:
> >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> >> >> > How do i convert this to vhdl? I have to use a concurrent
> statement
> >> as
>
> >> >> Q <= Q_int when rst = '0' else '0';
>
> >> >Hi,
>
> >> >I am having simulation problems with my code. I am trying to convert
> >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> >> >change at all. Please let me know what the problem could be.
>
> >> Remove the line:
>
> >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> >> after the BEGIN of the architecture.- Hide quoted text -
>
> >> - Show quoted text -
>
> >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> >"00";
>
> Sorry, my bad. I read your code too quickly, and thought you were
> assigning to Q in the clocked precess as well.
>
> Try:
> Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> Or better:
> Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> - Show quoted text -
neither one works. I am still having the same problem
Reply by RCIngham●December 7, 20072007-12-07
>On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
>> >> Anuja wrote:
>> >> > assign Q = (rst==0)?Q_int:1'do;
>>
>> >> > How do i convert this to vhdl? I have to use a concurrent
statement
>> as
>>
>> >> Q <= Q_int when rst = '0' else '0';
>>
>> >Hi,
>>
>> >I am having simulation problems with my code. I am trying to convert
>> >Verilog code to VHDL. I can compile correctly. When i simulate the
>> >following code in VHDL, value of Q_int is stuck at "00". It does not
>> >change at all. Please let me know what the problem could be.
>>
>> Remove the line:
>>
>> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>>
>> after the BEGIN of the architecture.- Hide quoted text -
>>
>> - Show quoted text -
>
>How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
>if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
>"00";
>
Sorry, my bad. I read your code too quickly, and thought you were
assigning to Q in the clocked precess as well.
Try:
Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
Or better:
Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);
Reply by Anuja●December 6, 20072007-12-06
On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> >> Anuja wrote:
> >> > assign Q = (rst==0)?Q_int:1'do;
>
> >> > How do i convert this to vhdl? I have to use a concurrent statement
> as
>
> >> Q <= Q_int when rst = '0' else '0';
>
> >Hi,
>
> >I am having simulation problems with my code. I am trying to convert
> >Verilog code to VHDL. I can compile correctly. When i simulate the
> >following code in VHDL, value of Q_int is stuck at "00". It does not
> >change at all. Please let me know what the problem could be.
>
> Remove the line:
>
> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> after the BEGIN of the architecture.- Hide quoted text -
>
> - Show quoted text -
How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
"00";
Reply by RCIngham●December 6, 20072007-12-06
>On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
>> Anuja wrote:
>> > assign Q = (rst==0)?Q_int:1'do;
>>
>> > How do i convert this to vhdl? I have to use a concurrent statement
as
>>
>> Q <= Q_int when rst = '0' else '0';
>
>Hi,
>
>I am having simulation problems with my code. I am trying to convert
>Verilog code to VHDL. I can compile correctly. When i simulate the
>following code in VHDL, value of Q_int is stuck at "00". It does not
>change at all. Please let me know what the problem could be.
>
Remove the line:
Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
after the BEGIN of the architecture.