Hello all,
I am trying to configure the ADC for voltage monitoring part.
I have to use only three channels, So I am using AV0, AV1 and AV2.
I am using Flash running at 8MHz to initialize and 40MHz is the fast
clock after initialization which I am using as analog system clock.
In SMARTGEN in the analog system builder I am selecting "ADC Sample
and Sequence Control only".
And I am only outputting ADC Results from the analog system.
In the post layout simulation, I see that Flash initialization is
done and I see ADC results as well as the three ADC Channels I am
configuring in my design. So post Layout simulation gives me perfect
result but the design does not give any result on DC Result in
reality.
In my design, I have used a Dual Port RAM as well that comprises 128
addresses of 16 bit wide data. I am reading out the ADC Results on to
the RAM memory but I see in POST LAYOUT Simulation perfect results but
do not see anything when I download the design on the board.
The design meets maximum delay timing requirements as well in the
timing analyzer.
Please help me if someone has suggestions.
On Jan 31, 11:11 pm, Rehman <iamreh...@gmail.com> wrote:
> On Jan 31, 4:46 pm, Kris Vorwerk <kris.vorw...@gmail.com> wrote:
>
> > > I am working on Actel Fusion FPGA.
> > > I am having problems with the ADC in my design.
>
> > > Can someone please help me with this?
>
> > More details please :)
>
> > (I'm not overly-familiar with the ADC, but if you provide a few more
> > details, either I or someone else may be able to help.)
>
> > K.
>
> Hey,
> I am trying to configure the ADC for voltage monitoring part.
> I have to use only three channels, So I am using AV0, AV1 and AV2.
> I am using Flash running at 8MHz to initialize and 40MHz is the fast
> clock after initialization which I am using as analog system clock.
> In SMARTGEN in the analog system builder I am selecting "ADC Sample
> and Sequence Control only".
> And I am only outputting ADC Results from the analog system.
>
> Te problem is that nothing comes out on the ADC Result.
> In the post layout simulation, I see that Flash initialization is
> done, but the ADC Channel and ADC Result is always zero along with
> ASSC_Done, ASSC_Wait, ChLAT, ChSAT signals.
>
> Out from the Analog system Block here is the code I use to read out
> the ADC Results.
>
> library ieee;
>
> library fusion;
>
> use IEEE.std_logic_1164.all;
>
> use IEEE.std_logic_signed.all;
>
> entity strm_ebs is
>
> port (
> ebs_right,ebs_up,ebs_left,ebs_down : out std_logic;
> rssi0,rssi1,rssi2,rssi3,rssi4,rfa0,rfa1,rfa2,rfa3,rfa4,
> rfb0,rfb1,rfb2,rfb3,rfb4 : out std_logic_vector (11 downto
> 0);
> adc_result : in std_logic_vector (11 downto 0);
> adc_ch : in std_logic_vector (4 downto 0); --adc channel
> adc_data_valid,clk_5k,reset : in std_logic
> );
>
> end strm_ebs;
>
> architecture arch_strm_ebs of strm_ebs is
>
> begin
>
> ---------Generating ebs signals -------------------
>
> Process (clk_5k,reset)
> variable ebs_sig : std_logic_vector (3 downto 0) := "0000";
> begin
>
> if reset='0' then
> ebs_sig := (others => '0');
> ebs_right <= '0';
> ebs_up <= '0';
> ebs_left <= '0';
> ebs_down <= '0';
> rssi0 <= (others => '0');
> rssi1 <= (others => '0');
> rssi2 <= (others => '0');
> rssi3 <= (others => '0');
> rssi4 <= (others => '0');
> rfa0 <= (others => '0');
> rfa1 <= (others => '0');
> rfa2 <= (others => '0');
> rfa3 <= (others => '0');
> rfa4 <= (others => '0');
> rfb0 <= (others => '0');
> rfb1 <= (others => '0');
> rfb2 <= (others => '0');
> rfb3 <= (others => '0');
> rfb4 <= (others => '0');
> elsif (clk_5k'event and clk_5k='1') then
>
> case ebs_sig is
> when "0000" =>
> ebs_sig := "0001";
> when "0001" =>
> ebs_sig := "0010";
> when "0010" =>
> ebs_sig := "0100";
> when "0100" =>
> ebs_sig := "1000";
> when "1000" =>
> ebs_sig := "0000";
> when others =>
> null;
> end case;
> ebs_right <= ebs_sig(3);
> ebs_up <= ebs_sig(2);
> ebs_left <= ebs_sig(1);
> ebs_down <= ebs_sig(0);
>
> if (adc_data_valid ='1') then
>
> case ebs_sig is
> when "0000" =>
> case adc_ch is
> when "00001" =>
> rfa0 <= adc_result;
> when "00100" =>
> rfb0 <= adc_result;
> when "00111" =>
> rssi0 <= adc_result;
> when others =>
> null;
> end case;
> when "0001" =>
> case adc_ch is
> when "00001" =>
> rfa4 <= adc_result;
> when "00100" =>
> rfb4 <= adc_result;
> when "00111" =>
> rssi4 <= adc_result;
> when others =>
> end case;
>
> when "0010" =>
> case adc_ch is
> when "00001" =>
> rfa3 <= adc_result;
> when "00100" =>
> rfb3 <= adc_result;
> when "00111" =>
> rssi3 <= adc_result;
> when others =>
> end case;
>
> when "0100" =>
> case adc_ch is
> when "00001" =>
> rfa2 <= adc_result;
> when "00100" =>
> rfb2 <= adc_result;
> when "00111" =>
> rssi2 <= adc_result;
> when others =>
> end case;
>
> when "1000" =>
> case adc_ch is
> when "00001" =>
> rfa1 <= adc_result;
> when "00100" =>
> rfb1 <= adc_result;
> when "00111" =>
> rssi1 <= adc_result;
> when others =>
> end case;
>
> when others =>
> null;
>
> end case; --end ebs signal cases
> end if; --if (adc_data_valid)
> end if; --if (reset)
>
> end process;
>
> ----------------------------------------------------
>
> ----------------------------------------------------
>
> end arch_strm_ebs;
>
> Thanks,
> Cheers!
Reply by Rehman●January 31, 20082008-01-31
On Jan 31, 4:46=A0pm, Kris Vorwerk <kris.vorw...@gmail.com> wrote:
> > I am working on Actel Fusion FPGA.
> > I am having problems with the ADC in my design.
>
> > Can someone please help me with this?
>
> More details please :)
>
> (I'm not overly-familiar with the ADC, but if you provide a few more
> details, either I or someone else may be able to help.)
>
> K.
Hey,
I am trying to configure the ADC for voltage monitoring part.
I have to use only three channels, So I am using AV0, AV1 and AV2.
I am using Flash running at 8MHz to initialize and 40MHz is the fast
clock after initialization which I am using as analog system clock.
In SMARTGEN in the analog system builder I am selecting "ADC Sample
and Sequence Control only".
And I am only outputting ADC Results from the analog system.
Te problem is that nothing comes out on the ADC Result.
In the post layout simulation, I see that Flash initialization is
done, but the ADC Channel and ADC Result is always zero along with
ASSC_Done, ASSC_Wait, ChLAT, ChSAT signals.
Out from the Analog system Block here is the code I use to read out
the ADC Results.
library ieee;
library fusion;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity strm_ebs is
port (
ebs_right,ebs_up,ebs_left,ebs_down : out std_logic;
rssi0,rssi1,rssi2,rssi3,rssi4,rfa0,rfa1,rfa2,rfa3,rfa4,
rfb0,rfb1,rfb2,rfb3,rfb4 : out std_logic_vector (11 downto
0);
adc_result : in std_logic_vector (11 downto 0);
adc_ch : in std_logic_vector (4 downto 0); --adc channel
adc_data_valid,clk_5k,reset : in std_logic
);
end strm_ebs;
architecture arch_strm_ebs of strm_ebs is
begin
---------Generating ebs signals -------------------
Process (clk_5k,reset)
variable ebs_sig : std_logic_vector (3 downto 0) :=3D "0000";
begin
if reset=3D'0' then
ebs_sig :=3D (others =3D> '0');
ebs_right <=3D '0';
ebs_up <=3D '0';
ebs_left <=3D '0';
ebs_down <=3D '0';
rssi0 <=3D (others =3D> '0');
rssi1 <=3D (others =3D> '0');
rssi2 <=3D (others =3D> '0');
rssi3 <=3D (others =3D> '0');
rssi4 <=3D (others =3D> '0');
rfa0 <=3D (others =3D> '0');
rfa1 <=3D (others =3D> '0');
rfa2 <=3D (others =3D> '0');
rfa3 <=3D (others =3D> '0');
rfa4 <=3D (others =3D> '0');
rfb0 <=3D (others =3D> '0');
rfb1 <=3D (others =3D> '0');
rfb2 <=3D (others =3D> '0');
rfb3 <=3D (others =3D> '0');
rfb4 <=3D (others =3D> '0');
elsif (clk_5k'event and clk_5k=3D'1') then
case ebs_sig is
when "0000" =3D>
ebs_sig :=3D "0001";
when "0001" =3D>
ebs_sig :=3D "0010";
when "0010" =3D>
ebs_sig :=3D "0100";
when "0100" =3D>
ebs_sig :=3D "1000";
when "1000" =3D>
ebs_sig :=3D "0000";
when others =3D>
null;
end case;
ebs_right <=3D ebs_sig(3);
ebs_up <=3D ebs_sig(2);
ebs_left <=3D ebs_sig(1);
ebs_down <=3D ebs_sig(0);
if (adc_data_valid =3D'1') then
case ebs_sig is
when "0000" =3D>
case adc_ch is
when "00001" =3D>
rfa0 <=3D adc_result;
when "00100" =3D>
rfb0 <=3D adc_result;
when "00111" =3D>
rssi0 <=3D adc_result;
when others =3D>
null;
end case;
when "0001" =3D>
case adc_ch is
when "00001" =3D>
rfa4 <=3D adc_result;
when "00100" =3D>
rfb4 <=3D adc_result;
when "00111" =3D>
rssi4 <=3D adc_result;
when others =3D>
end case;
when "0010" =3D>
case adc_ch is
when "00001" =3D>
rfa3 <=3D adc_result;
when "00100" =3D>
rfb3 <=3D adc_result;
when "00111" =3D>
rssi3 <=3D adc_result;
when others =3D>
end case;
when "0100" =3D>
case adc_ch is
when "00001" =3D>
rfa2 <=3D adc_result;
when "00100" =3D>
rfb2 <=3D adc_result;
when "00111" =3D>
rssi2 <=3D adc_result;
when others =3D>
end case;
when "1000" =3D>
case adc_ch is
when "00001" =3D>
rfa1 <=3D adc_result;
when "00100" =3D>
rfb1 <=3D adc_result;
when "00111" =3D>
rssi1 <=3D adc_result;
when others =3D>
end case;
when others =3D>
null;
end case; --end ebs signal cases
end if; --if (adc_data_valid)
end if; --if (reset)
end process;
----------------------------------------------------
----------------------------------------------------
end arch_strm_ebs;
Thanks,
Cheers!
Reply by Kris Vorwerk●January 31, 20082008-01-31
> I am working on Actel Fusion FPGA.
> I am having problems with the ADC in my design.
>
> Can someone please help me with this?
More details please :)
(I'm not overly-familiar with the ADC, but if you provide a few more
details, either I or someone else may be able to help.)
K.
Reply by Rehman●January 31, 20082008-01-31
Hello,
I am working on Actel Fusion FPGA.
I am having problems with the ADC in my design.
Can someone please help me with this?
Thanks alot!
Cheers!