On Feb 5, 5:04 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Feb 5, 4:52 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
>
>
>
> > FPGA wrote:
> > > I just found out that the packages in ieee_proposed that I added in
> > > the work dir are huge and thats what is causing the problem.
>
> > Glad you figured it out.
>
> > > Please
> > > suggest on how to add this library and also if I would still get the
> > > same problems with the size even after adding the packages into a
> > > library
>
> > It won't matter where the library is.
> > You are over the limit of the student license,
> > once you compile it into any library.
> > Pick a simpler project or call Mentor.
>
> > -- Mike Treseler
>
> Which tol do you suggest I use. I work on VHDL and Verilog. I need
> something very basic.
Some companies, for example Xilinx, have full-featured products (i.e.
high-demo boards) at very low prices. Perhaps Mentor or some other
simulator company would be able to help you.
HTH
-Dave Pollum
Reply by FPGA●February 5, 20082008-02-05
On Feb 5, 4:52=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> FPGA wrote:
> > I just found out that the packages in ieee_proposed that I added in
> > the work dir are huge and thats what is causing the problem.
>
> Glad you figured it out.
>
> > Please
> > suggest on how to add this library and also if I would still get the
> > same problems with the size even after adding the packages into a
> > library
>
> It won't matter where the library is.
> You are over the limit of the student license,
> once you compile it into any library.
> Pick a simpler project or call Mentor.
>
> =A0 =A0 =A0 =A0-- Mike Treseler
Which tol do you suggest I use. I work on VHDL and Verilog. I need
something very basic.
Reply by Mike Treseler●February 5, 20082008-02-05
FPGA wrote:
> I just found out that the packages in ieee_proposed that I added in
> the work dir are huge and thats what is causing the problem.
Glad you figured it out.
> Please
> suggest on how to add this library and also if I would still get the
> same problems with the size even after adding the packages into a
> library
It won't matter where the library is.
You are over the limit of the student license,
once you compile it into any library.
Pick a simpler project or call Mentor.
-- Mike Treseler
Reply by FPGA●February 5, 20082008-02-05
On Feb 5, 2:20=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> FPGA wrote:
> > # ** Warning: Design size of 10053 statements or 1 leaf instances
> > exceeds ModelSim PE Student Edition recommended capacity.
> > # Expect performance to be quite adversely affected.
> > How do I fix this problem?
>
> Remove 53 lines or buy a license.
>
> =A0 =A0 =A0 -- Mike Treseler
I want to add the ieee_proposed library which can be found at
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html . I
was
unsuccessfull in adding it the last time, so I just copy pasted the
files in the current work directory. Now, I am getting warnings that
# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
I just found out that the packages in ieee_proposed that I added in
the work dir are huge and thats what is causing the problem. Please
suggest on how to add this library and also if I would still get the
same problems with the size even after adding the packages into a
library
Thanks
Reply by Mike Treseler●February 5, 20082008-02-05
FPGA wrote:
> # ** Warning: Design size of 10053 statements or 1 leaf instances
> exceeds ModelSim PE Student Edition recommended capacity.
> # Expect performance to be quite adversely affected.
> How do I fix this problem?
Remove 53 lines or buy a license.
-- Mike Treseler
Reply by FPGA●February 5, 20082008-02-05
I am getting the following warning in Modelsim
# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
When I run simulations, I do not see any waveforms and it just freezes
there forever. My design size if around 1000 lines. I do have other
vhdl files for other projects. I have Modelsim Student edition.
How do I fix this problem?
Thanks