On 20 Feb., 12:21, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:
> On 2008-02-20, Jeff Cunningham <j...@sover.net> wrote:
>
> > I thought the whole point of the DCR was to allow control/status
> > accesses from the PPC to go on in parallel with PLB operations. If you
> > have to go through a PLB bridge, then the advantage of the DCR is lost.
>
> Personally I thought the idea was that the DCR bus is relatively slow
> and it should therefore be easy to meet timing on it even if we have many
> components connected to it. Stuff like parallel ports, uarts, performance
> monitors, configuration interfaces, etc could sit on the DCR bus in order
> to make it easier to meet tight timing constraints on the PLB bus.
>
> /Andreas

yes,
and for me I was about to convert a PPC design to microblaze for
Virtex-5LXT and the IP-Core used DCR so i had to use the bridge for
DCR

Antti

Antti wrote:

>>> DCR and OPB is gone.

>> DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use
>> those in 9.2 or beyond???
>>
>> -Jeff
> 
> do not worry, you can use PLB2DCR bridge
> I was about to make the verification of SATA Device IP core that was
> connected to old PPC SoC
> with MB 7.0 the DCR would go via bridge thats all, no problems as such
> 
> Antti

I thought the whole point of the DCR was to allow control/status 
accesses from the PPC to go on in parallel with PLB operations. If you 
have to go through a PLB bridge, then the advantage of the DCR is lost.

-Jeff

On 2008-02-20, Jeff Cunningham <jcc@sover.net> wrote:
> I thought the whole point of the DCR was to allow control/status 
> accesses from the PPC to go on in parallel with PLB operations. If you 
> have to go through a PLB bridge, then the advantage of the DCR is lost.

Personally I thought the idea was that the DCR bus is relatively slow
and it should therefore be easy to meet timing on it even if we have many
components connected to it. Stuff like parallel ports, uarts, performance
monitors, configuration interfaces, etc could sit on the DCR bus in order
to make it easier to meet tight timing constraints on the PLB bus.

/Andreas

On 19 Feb., 21:16, Jeff Cunningham <j...@sover.net> wrote:
> Guru wrote:
> >> Ales,
> >> I'm still on 9.1. What bus diversity is changed in 9.2?
> >> -Jeff
>
> > DCR and OPB is gone.
>
> > Guru
>
> DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use
> those in 9.2 or beyond???
>
> -Jeff

do not worry, you can use PLB2DCR bridge
I was about to make the verification of SATA Device IP core that was
connected to old PPC SoC
with MB 7.0 the DCR would go via bridge thats all, no problems as such

Antti

Guru wrote:
>> Ales,
>> I'm still on 9.1. What bus diversity is changed in 9.2?
>> -Jeff
> 
> DCR and OPB is gone.
> 
> Guru

DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use 
those in 9.2 or beyond???

-Jeff

On Feb 18, 5:20=A0pm, Jeff Cunningham <j...@sover.net> wrote:
> Guru wrote:
> > I had FX12 totally full, with only 2 point-to-point PLB busses
> > connected to MPMC2 and PPC. For access to peripherals I used
> > exclusively DCR (low logic resources and high responsiveness), for
> > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
> > I recommend NPI for very high DMA bandwidth.
>
> > Too bad that with EDK 9.2 the bus diversity is gone. You have to to
> > use PLB in all cases.
>
> Ales,
> I'm still on 9.1. What bus diversity is changed in 9.2?
> -Jeff

DCR and OPB is gone.

Guru

Antti wrote:
> On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote:
> 
>>Guru wrote:
>>
>>>I had FX12 totally full, with only 2 point-to-point PLB busses
>>>connected to MPMC2 and PPC. For access to peripherals I used
>>>exclusively DCR (low logic resources and high responsiveness), for
>>>high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
>>>I recommend NPI for very high DMA bandwidth.
>>
>>>Too bad that with EDK 9.2 the bus diversity is gone. You have to to
>>>use PLB in all cases.
>>
>>Ales,
>>I'm still on 9.1. What bus diversity is changed in 9.2?
>>-Jeff
> 
> 
> Microblaze 7.0 doesnt have OPB bus anymore.
> was a real shock !
> 
> Old designs still can be used.
> But all new systems have all new IP-Cores!

  So much for the often-vaunted claims of 'design longevity' when
using SoftCPU cores then !  ;)
  Seems to have caught the Software Version Creep disease.... ?

-jg

On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote:
> Guru wrote:
> > I had FX12 totally full, with only 2 point-to-point PLB busses
> > connected to MPMC2 and PPC. For access to peripherals I used
> > exclusively DCR (low logic resources and high responsiveness), for
> > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
> > I recommend NPI for very high DMA bandwidth.
>
> > Too bad that with EDK 9.2 the bus diversity is gone. You have to to
> > use PLB in all cases.
>
> Ales,
> I'm still on 9.1. What bus diversity is changed in 9.2?
> -Jeff

Microblaze 7.0 doesnt have OPB bus anymore.
was a real shock !

Old designs still can be used.
But all new systems have all new IP-Cores!

Antti

Guru wrote:
> I had FX12 totally full, with only 2 point-to-point PLB busses
> connected to MPMC2 and PPC. For access to peripherals I used
> exclusively DCR (low logic resources and high responsiveness), for
> high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
> I recommend NPI for very high DMA bandwidth.
> 
> Too bad that with EDK 9.2 the bus diversity is gone. You have to to
> use PLB in all cases.

Ales,
I'm still on 9.1. What bus diversity is changed in 9.2?
-Jeff

On Feb 17, 7:39=A0pm, Jeff Cunningham <j...@sover.net> wrote:
> Stephen,
>
> I have had no trouble running a 2/3 full FX12-10 PLB bus with 4 devices
> at 100 Mhz.
>
> If you have a lot of random control/status type register access from the
> CPU, you can offload that onto the DCR bus. And try to use as large as
> possible burst transfers on the PLB bus.
>
> -Jeff

I had FX12 totally full, with only 2 point-to-point PLB busses
connected to MPMC2 and PPC. For access to peripherals I used
exclusively DCR (low logic resources and high responsiveness), for
high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
I recommend NPI for very high DMA bandwidth.

Too bad that with EDK 9.2 the bus diversity is gone. You have to to
use PLB in all cases.

Cheers,

Ales