On Feb 27, 1:22 am, antti.tyrvai...@luukku.com wrote:
> On 27 helmi, 00:45, George <whuste...@gmail.com> wrote:
>
> > I really appreciate if anyone can tell. Thanks
> > George
>
> Why you don't convert your source files (VHDL, Verilog) to Xilinx?
>
> Antti

My situation is I don't have the source files. I just want to deal
with the P&R circuit.

On 27 helmi, 00:45, George <whuste...@gmail.com> wrote:
> I really appreciate if anyone can tell. Thanks
> George
>

Why you don't convert your source files (VHDL, Verilog) to Xilinx?

Antti

I really appreciate if anyone can tell. Thanks
George

On Feb 26, 12:12 am, "=C9=B5=B9=CF" <whuste...@gmail.com> wrote:
> Hi:
>    Does anyone know whether Altera has some analogous file like XDL of
> Xilinx so that we can read the place and route of the circuit of
> Altera's FPGA textually?
>    If not, I wonder whether there is a third tool that can generate an
> intermediate file so that it can accomplish this process: Altera FPGA
> circuit (Placed and Routed) <-->intermediate file<-->Xilinx FPGA
> circuit (Placed and Routed).
>
> Thanks.
> George

Hi:
   Does anyone know whether Altera has some analogous file like XDL of
Xilinx so that we can read the place and route of the circuit of
Altera's FPGA textually?
   If not, I wonder whether there is a third tool that can generate an
intermediate file so that it can accomplish this process: Altera FPGA
circuit (Placed and Routed) <-->intermediate file<-->Xilinx FPGA
circuit (Placed and Routed).

Thanks.
George