> My project has several ADC channels with 16bit data up to 24kSPS.
>
> There is no need for each ADC sample to be sent ASAP to the
> microblaze, as the data is processed in chunks of 200 samples. A
> previous (non-xilinx) version of this project used a FIFO and a burst
> read over a PCI bus to a pentium processor.
>
> Now, reading about FSL it seems that the microblaze has to execute an
> instruction to get every sample of data?
> What I want is the lowest overhead - given that I can use a FIFO,
> would the FIFO with DMA route be better suited to my needs than FSL?
As of EDK9.2, there is an plb2fsl_bridge, basically a single channel
bridge between the PLB and FSL. So,. combine that with an
xps_central_dma and you can DMA directly to an FSL-based peripheral.
I really like FSL but the requirement for all data to pass through the
CPU is a performance problem, particularly in OS environments such as
Linux. Standalone dedicated apps maybe not so bad. If the data is
truly sourcing or sinking in the CPU, then direct FSL is OK. But, if
memory is your source or sink, DMA is necessary.
Regards,
John
Reply by Martin Thompson●March 19, 20082008-03-19
markmcmahon@hotmail.com writes:
>> Where are you going to DMA to? �Won't the processor need to execute an
>> instruction to access every sample of data then as well? �And wait the
>> memory latency (if any).
>>
>> Personally, I would use a FIFO on the FSL. �It seems a lot simpler
>> than DMA!
>>
<snip q's on adding FIFOs, I hope G�ran answered those :-)>
>
> As to the overhead, I'm assuming I would get one interrupt per 200
> samples from the FIFO instead of servicing 200 interrupts from the
> FSL.
If your processing is sequential (sorry, I've assumed up 'til now that
it was), you set up your FSL hardware to interrupt you when you have
enough data, so 200 samples in your case. At that point, you can run
your processing routine. No *extra* data transfers are required, you
just read a sample from the FSL and process it.
If you need random access to your 200 samples, then use one port of a
dual port BRAM to store the samples from your peripheral directly.
You can then interrupt the processor when it's done and have fast
random access to the BRAM via the local memory bus (LMB). No FIFO, no
FSL, just memory. It is DMA of a sort, but you've got a private
dedicated port for your data gathering peripheral, so a lot less
hassle than doing bus-mastering on a shared bus.
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply by ●March 18, 20082008-03-18
Hi,
The FSL bus has parameters which allows you to specify the size and what
kind of FIFO you want.
This is from the FSL_v2_11_a datasheet
C_FSL_DEPTH
Specifies the depth of the FIFO implemented by the FSL bus. The depth can be
as low as 1 or as high as
8192. The depth that can be specified is dependent on the implementation
scheme of the FIFO. When
the parameter C_ASYNC_CLKS is set to 0, the depth allowed is between 1 and
8192. When the
parameter C_ASYNC_CLKS is set to 1 and C_IMPL_STYLE is set to 0 (LUT RAM),
the depth allowed
is between 16 and 128. When the parameter C_ASYNC_CLKS is set to 1 and
C_IMPL_STYLE is set to 1
(BRAM), the depth allowed is between 512 and 8192.
C_USE_CONTROL
Specifies whether or not the control bit is propagated along with the data
bit. When set to 1, the control
bit is transmitted from master to slave interface. When set to 0, the
control bit transmitted to the slave
is 0. Setting this bit to 0 when propagation of control bit is not required;
enables reduction in the area of
the FSL bus.
C_ASYNC_CLKS
Specifies whether the FIFO in the FSL bus is implemented as a synchronous
FIFO or asynchronous
FIFO. When set to 1, the FSL implements an asynchronous FIFO. In this case,
the clock ports
FSL_M_Clk and FSL_S_Clk are used as the master and slave clocks. If set to
0, the FSL is implemented
as a synchronous FIFO. In this case, the clock port FSL_Clk is used for both
the master and slave
interfaces.
C_IMPL_STYLE
Specifies the style of implementation of the FIFO of the FSL. If set to 1,
the FIFO is implemented using
BRAMs. If set to 0, the FIFO is implemented using LUT RAMs. This parameter
affects timing: When
C_IMPL_STYLE=1, there is a one-cycle fall-through latency from a write to an
empty FIFO before FSL_S_Exists
G�ran
<markmcmahon@hotmail.com> wrote in message
news:64f56d76-50a2-433c-992a-3b230987bca3@i12g2000prf.googlegroups.com...
> Where are you going to DMA to? Won't the processor need to execute an
> instruction to access every sample of data then as well? And wait the
> memory latency (if any).
>
> Personally, I would use a FIFO on the FSL. It seems a lot simpler
> than DMA!
>
How would I add a FIFO to the FSL? I have read that FSL is FIFO
based, but can I parameterize it? (Do you mean add another FIFO or
use the one in the FSL?)
http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf
page 7.
I am using the "Create or import peripheral" wizard but I haven't
looked at any FSL VHDL yet.
As to the overhead, I'm assuming I would get one interrupt per 200
samples from the FIFO instead of servicing 200 interrupts from the
FSL.
Thanks for your help.
Reply by ●March 18, 20082008-03-18
> Where are you going to DMA to? =A0Won't the processor need to execute an
> instruction to access every sample of data then as well? =A0And wait the
> memory latency (if any).
>
> Personally, I would use a FIFO on the FSL. =A0It seems a lot simpler
> than DMA!
>
How would I add a FIFO to the FSL? I have read that FSL is FIFO
based, but can I parameterize it? (Do you mean add another FIFO or
use the one in the FSL?)
http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf
page 7.
I am using the "Create or import peripheral" wizard but I haven't
looked at any FSL VHDL yet.
As to the overhead, I'm assuming I would get one interrupt per 200
samples from the FIFO instead of servicing 200 interrupts from the
FSL.
Thanks for your help.
Reply by Martin Thompson●March 18, 20082008-03-18
markmcmahon@hotmail.com writes:
> Hello everyone,
>
> My project has several ADC channels with 16bit data up to 24kSPS.
>
> There is no need for each ADC sample to be sent ASAP to the
> microblaze, as the data is processed in chunks of 200 samples. A
> previous (non-xilinx) version of this project used a FIFO and a burst
> read over a PCI bus to a pentium processor.
>
> Now, reading about FSL it seems that the microblaze has to execute an
> instruction to get every sample of data?
Yes. But so did the Pentium...
> What I want is the lowest overhead - given that I can use a FIFO,
> would the FIFO with DMA route be better suited to my needs than FSL?
Where are you going to DMA to? Won't the processor need to execute an
instruction to access every sample of data then as well? And wait the
memory latency (if any).
Personally, I would use a FIFO on the FSL. It seems a lot simpler
than DMA!
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply by ●March 18, 20082008-03-18
> Do you mean the lowest hardware overhead, the lowest software overhead, or
> something else?
The lowest software overhead - i.e. I want to maximise the time the
processor has to do the number crunching, and minimise the amount of
time the processor is moving data around.
Given the above, I'm thinking that the FIFO would generate an
interrupt when nearly full, the processor would set up the DMA
transaction and the DMA would interrupt microblaze when completed.
With FSL I'd need to execute a FSL instruction for each sample.
Reply by Brian Drummond●March 18, 20082008-03-18
On Tue, 18 Mar 2008 02:28:23 -0700 (PDT), markmcmahon@hotmail.com wrote:
>Hello everyone,
>
>My project has several ADC channels with 16bit data up to 24kSPS.
>
>There is no need for each ADC sample to be sent ASAP to the
>microblaze, as the data is processed in chunks of 200 samples. A
>previous (non-xilinx) version of this project used a FIFO and a burst
>read over a PCI bus to a pentium processor.
>
>Now, reading about FSL it seems that the microblaze has to execute an
>instruction to get every sample of data?
>What I want is the lowest overhead - given that I can use a FIFO,
>would the FIFO with DMA route be better suited to my needs than FSL?
Do you mean the lowest hardware overhead, the lowest software overhead, or
something else?
This might affect the answer.
- Brian
Reply by ●March 18, 20082008-03-18
Hello everyone,
My project has several ADC channels with 16bit data up to 24kSPS.
There is no need for each ADC sample to be sent ASAP to the
microblaze, as the data is processed in chunks of 200 samples. A
previous (non-xilinx) version of this project used a FIFO and a burst
read over a PCI bus to a pentium processor.
Now, reading about FSL it seems that the microblaze has to execute an
instruction to get every sample of data?
What I want is the lowest overhead - given that I can use a FIFO,
would the FIFO with DMA route be better suited to my needs than FSL?
Thanks,
Mark.