Hello,

I currently working on a project in EDK 9.1.
I have a PPC system with a custom peripheral the is connected to the
PPC through FSL->FCB->APU.

If I create an EDK project using microblaze and integrate my
peripheral I can read an write to my peripheral and all the data it
computes is correct.

Using the same peripheral (integrate my custom peripheral with the
coprocessor wizard) in an EDK project that uses PPC I run in some
problems:
( To clarify I developed the drivers for my custom peripheral using
the driver templates generated by the "create peripheral wizard")
When i create a stand alone application  and use the drivers is have
to include a "usleep(1);" after every read or write
( fslput() or fslget() )to the bus. otherwise the data on the bus is
sometimes corrupt.

But when I create a software project that uses Xilkernel my peripheral
doesn't work anymore. It looks somehow that the data written to and
read from is is always corrupted even with the wait cycles...

does anyone have a hint for me?

I found some older post about the apu and fsl here (http://
groups.google.at/group/comp.arch.fpga/browse_thread/thread/
416bd68f00233500/b2bb54d16112f204?lnk=st&q=APU+MSR
+FSL#b2bb54d16112f204)
but unfortunately I don't know about what patch they are talking
about.


The code I use to initialize the apu is:

	unsigned int msr_data;
	msr_data = mfmsr();
	msr_data = msr_data | XREG_MSR_APU_AVAILABLE | XREG_MSR_APU_ENABLE;
	mtmsr(msr_data);
        .........
        xilkernel_main();

BTW: I found in the XIlinx data sheets that these bit should be set to
0 because they are not supported?? whats that all about? I found this
piece of code in another sample project an for the standalone PPC
project this works. Do I have to use another initialization for the
xilkernel?

Thanks Urban