Reply by jjli...@hotmail.com●May 20, 20082008-05-20
On May 20, 10:02 am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:
> Hello, I know many will say this is not an appropriate group to post
> such a question, but I wasn't getting any response on the Verilog
> group, so please let me apologize. I am new to Verilog and need some
> help instantiating a lpm dcfifo in my code. Here is what I have so
> far:
>
> FIFIN : lpm_fifo_dc WITH (LPM_WIDTH = 64, LPM_NUMWORDS = 64,
> LPM_WIDTHU = 9, RDSYNC_DELAYPIPE = 3, WRSYNC_DELAYPIPE = 3);
>
> FIFIN.aclr = (!rstn);
> FIFIN.wrclock = (clk);
> FIFIN.wrreq = (wr_fiforeq);
> FIFIN.data[31..0] = (dma_wrdata);
> FIFIN.rdclock = (clk);
> FIFIN.rdreq = (dma1_rddata);
> FIFIN.q = (rd_fiforeq);
>
> If anyone has some examples of instantiating a lpm function within
> Verilog I would greatly appreciate your help.
>
> Thanks,
> joe
Reply by jjli...@hotmail.com●May 20, 20082008-05-20
Hello, I know many will say this is not an appropriate group to post
such a question, but I wasn't getting any response on the Verilog
group, so please let me apologize. I am new to Verilog and need some
help instantiating a lpm dcfifo in my code. Here is what I have so
far:
FIFIN : lpm_fifo_dc WITH (LPM_WIDTH = 64, LPM_NUMWORDS = 64,
LPM_WIDTHU = 9, RDSYNC_DELAYPIPE = 3, WRSYNC_DELAYPIPE = 3);
FIFIN.aclr = (!rstn);
FIFIN.wrclock = (clk);
FIFIN.wrreq = (wr_fiforeq);
FIFIN.data[31..0] = (dma_wrdata);
FIFIN.rdclock = (clk);
FIFIN.rdreq = (dma1_rddata);
FIFIN.q = (rd_fiforeq);
If anyone has some examples of instantiating a lpm function within
Verilog I would greatly appreciate your help.
Thanks,
joe