"FP" <FPGA.unknown@gmail.com> wrote in message 
news:c1b1e317-7bf9-48ad-af6f-4d46444e4c7a@a1g2000hsb.googlegroups.com...
>I would like some suggestions on interfacing the Xilinx Spartan3
> device with a DDR SDRAM. The idea is to build a controller that will
> set up the DDR-SDRAM so that I can do a burst read of a page of data
> into a block of internal SRAM (dual port).
>
> Your help is appreciated

STW or at least Xilinx's website.

http://www.xilinx.com/products/devkits/HW-SPAR3ADDR2-DK-UNI-G.htm

On Jun 5, 7:24 am, FP <FPGA.unkn...@gmail.com> wrote:
> I would like some suggestions on interfacing the Xilinx Spartan3
> device with a DDR SDRAM. The idea is to build a controller that will
> set up the DDR-SDRAM so that I can do a burst read of a page of data
> into a block of internal SRAM (dual port).
>
> Your help is appreciated


Xilinx has several design examples on their web site.

A google search turns up a few more on various sites.

You do know about burst length limitations with DDR devices?  You
can't burst a full page.

G.

I would like some suggestions on interfacing the Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).

Your help is appreciated