I'am always open for new ideas how to code certain things, but for now
I will probably stick with my code (since I've written small software
to automatically generate VHDL for certain input/output frequencies),
in future I will probably switch to Verilog and update files on my
page with Verilog files instead of VHDL. But such suggestions are
always helpful and welcome :)

Regards

Newman napisa=C5=82(a):
> On Jul 22, 7:23=EF=BF=BDpm, langw...@fonz.dk wrote:
> > On 22 Jul., 17:00, Newman <newman5...@yahoo.com> wrote:
> >
> >
> >
> >
> >
> > > On Jul 22, 9:43 am, Mike Treseler <mtrese...@gmail.com> wrote:
> >
> > > > mike wrote:
> > > > >>>> A better design would use clk here
> > > > >>>> and make baudTick a clock enable.
> > > > wojtek wrote:
> > > > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get ho=
w the
> > > > >>> phase accumulator works, trust me it is ok the way it is.
> >
> > > > I get the phase accumulator,
> > > > but why bother with the fussy DCM at all?
> >
> > > > Newman wrote:
> > > > >> Some people cringe when they see a register output used as an
> > > > >> input clock to other synchronous logic and will go to great leng=
ths to
> > > > >> avoid it because they might have to explain why this will never =
cause
> > > > >> a timing issue.
> >
> > > > I avoid it because
> > > > I prefer writing code
> > > > to writing clock domain constraints.
> >
> > > > > Since most DCM's aren't able to create a frequency
> > > > > of less than 10MHz, using phase accumulator to do it is pretty go=
od
> > > > > idea (and it will be quite precise as well).
> >
> > > > I agree.
> > > > So why did you punt it?
> > > > A phase accumulator is portable, flexible and a precise as I need.
> > > > See also:http://groups.google.com/groups/search?q=3Daccum_s
> >
> > > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD -- Mike Treseler
> >
> > > Hi Wojtek
> >
> > > =EF=BF=BD I noted with "-- Look Here ZZZ" comments where preliminary =
changes
> > > could be
> > > investigated to eliminate a clock domain. =EF=BF=BDbaudTick becomes a
> > > synchronously delayed
> > > version of phaseAcc(phaseAccWidth) and can be used to detect the
> > > rising edge of
> > > phaseAcc(phaseAccWidth) after a =EF=BF=BDclock cycle delay. =EF=BF=BD=
I did not
> > > simulate it or anything.
> >
> > > -- baud generator based on phase accumulator
> > > =EF=BF=BD baudTickGen : process (clk) is begin
> > > =EF=BF=BD =EF=BF=BD if(rising_edge(clk))then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD phaseAcc <=3D phaseAcc + phaseAccTuning=
;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD baudTick <=3D phaseAcc(phaseAccWidth); =
=EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD-- Look Here ZZZ
> > > =EF=BF=BD =EF=BF=BD end if;
> > > =EF=BF=BD end process baudTickGen;
> > > =EF=BF=BD -- MSB of phase accumulator generates the proper baud rate
> > > =EF=BF=BD -- Look Here ZZZ baudTick <=3D phaseAcc(phaseAccWidth);
> >
> > > =EF=BF=BD -- transmitter: 8 bits of data, no parity control, 1 stop b=
it
> > > =EF=BF=BD -- Look Here ZZZ transmitter : process (baudTick) is begin
> > > =EF=BF=BD transmitter : process (clk) is begin =EF=BF=BD-- Look Here
> >
> > > =EF=BF=BD =EF=BF=BD -- Look HereZZZ =EF=BF=BDif(rising_edge(baudTick)=
)then
> > > =EF=BF=BD =EF=BF=BD if((baudTick =3D '0') and (phaseAcc(phaseAccWidth=
) =3D '1')) then =EF=BF=BD --
> > > Look Here ZZZ
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD showtick <=3D'1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD if(reset =3D '1')then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD state <=3D 0;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD dataBuffer <=3D (others =3D> =
'0');
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD else
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD if(state =3D 0 and startTxD =
=3D '0')then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD busyTxD <=3D '0';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD TxD <=3D '1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD elsif(state =3D 0 and startTx=
D =3D '1')then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD TxD <=3D '0';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD dataBuffer <=3D dat=
aTxD;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD busyTxD <=3D '1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD state <=3D state + =
1;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD elsif(state > 0 and state < 9=
)then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD busyTxD <=3D '1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD TxD <=3D dataBuffer=
(state-1);
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD state <=3D state + =
1;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD elsif(state =3D 9)then
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD TxD <=3D '1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD busyTxD <=3D '1';
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD state <=3D 0;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD end if;
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD end if;
> >
> > > =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BDend if;
> > > =EF=BF=BD end process;
> >
> > > end TxD_arch;
> >
> > it's been far too long since I've written any VHDL, but I verilog I
> > would do it like this:
> >
> > reg =EF=BF=BD[phaseAccWidth-1:0] phaseAcc;
> > reg =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=
=BD =EF=BF=BD =EF=BF=BD =EF=BF=BD =EF=BF=BDbaudTick;
> >
> > always@(posedge clk or rstb)
> > =EF=BF=BDif(!rstb)
> > =EF=BF=BD =EF=BF=BD {baudTick,phaseAcc} <=3D 0;
> > =EF=BF=BDelse
> > =EF=BF=BD =EF=BF=BD {baudTick,phaseAcc} <=3D {1'd0,phaseAcc} + phaseAcc=
Tuning;
> >
> > ....
> >
> > -Lasse- Hide quoted text -
> >
> > - Show quoted text -
>
> Hi Lasse,
>   It would appear that your way is clever.  It looks to generates a
> clock enable pulse on the overflow which would appear to happen only
> for one clk cycle, and it also has a reset which would make the
> simulation a easier.  Took me a minute to determine what you were
> doing.
>
>   I did not mean to get involved with recoding the designer's file.  I
> thought there was some communications snafu of what was meant by using
> baudTick as a clock enable. My attempt was to try to give a little
> better understanding of what was involved and kindof show that it was
> not a big change.  I think your code does this better.  With that, I
> shall exit this thread
>
> -Regards
>
> Newman
>
> -Newman

On Jul 22, 7:23=A0pm, langw...@fonz.dk wrote:
> On 22 Jul., 17:00, Newman <newman5...@yahoo.com> wrote:
>
>
>
>
>
> > On Jul 22, 9:43 am, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > mike wrote:
> > > >>>> A better design would use clk here
> > > >>>> and make baudTick a clock enable.
> > > wojtek wrote:
> > > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how =
the
> > > >>> phase accumulator works, trust me it is ok the way it is.
>
> > > I get the phase accumulator,
> > > but why bother with the fussy DCM at all?
>
> > > Newman wrote:
> > > >> Some people cringe when they see a register output used as an
> > > >> input clock to other synchronous logic and will go to great length=
s to
> > > >> avoid it because they might have to explain why this will never ca=
use
> > > >> a timing issue.
>
> > > I avoid it because
> > > I prefer writing code
> > > to writing clock domain constraints.
>
> > > > Since most DCM's aren't able to create a frequency
> > > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > > idea (and it will be quite precise as well).
>
> > > I agree.
> > > So why did you punt it?
> > > A phase accumulator is portable, flexible and a precise as I need.
> > > See also:http://groups.google.com/groups/search?q=3Daccum_s
>
> > > =A0 =A0 =A0 =A0 -- Mike Treseler
>
> > Hi Wojtek
>
> > =A0 I noted with "-- Look Here ZZZ" comments where preliminary changes
> > could be
> > investigated to eliminate a clock domain. =A0baudTick becomes a
> > synchronously delayed
> > version of phaseAcc(phaseAccWidth) and can be used to detect the
> > rising edge of
> > phaseAcc(phaseAccWidth) after a =A0clock cycle delay. =A0I did not
> > simulate it or anything.
>
> > -- baud generator based on phase accumulator
> > =A0 baudTickGen : process (clk) is begin
> > =A0 =A0 if(rising_edge(clk))then
> > =A0 =A0 =A0 phaseAcc <=3D phaseAcc + phaseAccTuning;
> > =A0 =A0 =A0 baudTick <=3D phaseAcc(phaseAccWidth); =A0 =A0 =A0 =A0-- Lo=
ok Here ZZZ
> > =A0 =A0 end if;
> > =A0 end process baudTickGen;
> > =A0 -- MSB of phase accumulator generates the proper baud rate
> > =A0 -- Look Here ZZZ baudTick <=3D phaseAcc(phaseAccWidth);
>
> > =A0 -- transmitter: 8 bits of data, no parity control, 1 stop bit
> > =A0 -- Look Here ZZZ transmitter : process (baudTick) is begin
> > =A0 transmitter : process (clk) is begin =A0-- Look Here
>
> > =A0 =A0 -- Look HereZZZ =A0if(rising_edge(baudTick))then
> > =A0 =A0 if((baudTick =3D '0') and (phaseAcc(phaseAccWidth) =3D '1')) th=
en =A0 --
> > Look Here ZZZ
> > =A0 =A0 =A0 =A0 showtick <=3D'1';
> > =A0 =A0 =A0 if(reset =3D '1')then
> > =A0 =A0 =A0 =A0 state <=3D 0;
> > =A0 =A0 =A0 =A0 dataBuffer <=3D (others =3D> '0');
> > =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 if(state =3D 0 and startTxD =3D '0')then
> > =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '0';
> > =A0 =A0 =A0 =A0 =A0 TxD <=3D '1';
> > =A0 =A0 =A0 =A0 elsif(state =3D 0 and startTxD =3D '1')then
> > =A0 =A0 =A0 =A0 =A0 TxD <=3D '0';
> > =A0 =A0 =A0 =A0 =A0 dataBuffer <=3D dataTxD;
> > =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> > =A0 =A0 =A0 =A0 =A0 state <=3D state + 1;
> > =A0 =A0 =A0 =A0 elsif(state > 0 and state < 9)then
> > =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> > =A0 =A0 =A0 =A0 =A0 TxD <=3D dataBuffer(state-1);
> > =A0 =A0 =A0 =A0 =A0 state <=3D state + 1;
> > =A0 =A0 =A0 =A0 elsif(state =3D 9)then
> > =A0 =A0 =A0 =A0 =A0 TxD <=3D '1';
> > =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> > =A0 =A0 =A0 =A0 =A0 state <=3D 0;
> > =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 end if;
>
> > =A0 =A0 =A0 =A0 =A0end if;
> > =A0 end process;
>
> > end TxD_arch;
>
> it's been far too long since I've written any VHDL, but I verilog I
> would do it like this:
>
> reg =A0[phaseAccWidth-1:0] phaseAcc;
> reg =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0baudTick;
>
> always@(posedge clk or rstb)
> =A0if(!rstb)
> =A0 =A0 {baudTick,phaseAcc} <=3D 0;
> =A0else
> =A0 =A0 {baudTick,phaseAcc} <=3D {1'd0,phaseAcc} + phaseAccTuning;
>
> ....
>
> -Lasse- Hide quoted text -
>
> - Show quoted text -

Hi Lasse,
  It would appear that your way is clever.  It looks to generates a
clock enable pulse on the overflow which would appear to happen only
for one clk cycle, and it also has a reset which would make the
simulation a easier.  Took me a minute to determine what you were
doing.

  I did not mean to get involved with recoding the designer's file.  I
thought there was some communications snafu of what was meant by using
baudTick as a clock enable. My attempt was to try to give a little
better understanding of what was involved and kindof show that it was
not a big change.  I think your code does this better.  With that, I
shall exit this thread

-Regards

Newman

-Newman

On 22 Jul., 17:00, Newman <newman5...@yahoo.com> wrote:
> On Jul 22, 9:43 am, Mike Treseler <mtrese...@gmail.com> wrote:
>
>
>
> > mike wrote:
> > >>>> A better design would use clk here
> > >>>> and make baudTick a clock enable.
> > wojtek wrote:
> > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > >>> phase accumulator works, trust me it is ok the way it is.
>
> > I get the phase accumulator,
> > but why bother with the fussy DCM at all?
>
> > Newman wrote:
> > >> Some people cringe when they see a register output used as an
> > >> input clock to other synchronous logic and will go to great lengths to
> > >> avoid it because they might have to explain why this will never cause
> > >> a timing issue.
>
> > I avoid it because
> > I prefer writing code
> > to writing clock domain constraints.
>
> > > Since most DCM's aren't able to create a frequency
> > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > idea (and it will be quite precise as well).
>
> > I agree.
> > So why did you punt it?
> > A phase accumulator is portable, flexible and a precise as I need.
> > See also:http://groups.google.com/groups/search?q=accum_s
>
> >         -- Mike Treseler
>
> Hi Wojtek
>
>   I noted with "-- Look Here ZZZ" comments where preliminary changes
> could be
> investigated to eliminate a clock domain.  baudTick becomes a
> synchronously delayed
> version of phaseAcc(phaseAccWidth) and can be used to detect the
> rising edge of
> phaseAcc(phaseAccWidth) after a  clock cycle delay.  I did not
> simulate it or anything.
>
> -- baud generator based on phase accumulator
>   baudTickGen : process (clk) is begin
>     if(rising_edge(clk))then
>       phaseAcc <= phaseAcc + phaseAccTuning;
>       baudTick <= phaseAcc(phaseAccWidth);        -- Look Here ZZZ
>     end if;
>   end process baudTickGen;
>   -- MSB of phase accumulator generates the proper baud rate
>   -- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);
>
>   -- transmitter: 8 bits of data, no parity control, 1 stop bit
>   -- Look Here ZZZ transmitter : process (baudTick) is begin
>   transmitter : process (clk) is begin  -- Look Here
>
>     -- Look HereZZZ  if(rising_edge(baudTick))then
>     if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then   --
> Look Here ZZZ
>         showtick <='1';
>       if(reset = '1')then
>         state <= 0;
>         dataBuffer <= (others => '0');
>       else
>         if(state = 0 and startTxD = '0')then
>           busyTxD <= '0';
>           TxD <= '1';
>         elsif(state = 0 and startTxD = '1')then
>           TxD <= '0';
>           dataBuffer <= dataTxD;
>           busyTxD <= '1';
>           state <= state + 1;
>         elsif(state > 0 and state < 9)then
>           busyTxD <= '1';
>           TxD <= dataBuffer(state-1);
>           state <= state + 1;
>         elsif(state = 9)then
>           TxD <= '1';
>           busyTxD <= '1';
>           state <= 0;
>         end if;
>       end if;
>
>          end if;
>   end process;
>
> end TxD_arch;


it's been far too long since I've written any VHDL, but I verilog I
would do it like this:

reg  [phaseAccWidth-1:0] phaseAcc;
reg                      baudTick;

always@(posedge clk or rstb)
 if(!rstb)
    {baudTick,phaseAcc} <= 0;
 else
    {baudTick,phaseAcc} <= {1'd0,phaseAcc} + phaseAccTuning;

....


-Lasse

On Jul 22, 11:00=A0am, Newman <newman5...@yahoo.com> wrote:
> On Jul 22, 9:43=A0am, Mike Treseler <mtrese...@gmail.com> wrote:
>
>
>
>
>
> > mike wrote:
> > >>>> A better design would use clk here
> > >>>> and make baudTick a clock enable.
> > wojtek wrote:
> > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how th=
e
> > >>> phase accumulator works, trust me it is ok the way it is.
>
> > I get the phase accumulator,
> > but why bother with the fussy DCM at all?
>
> > Newman wrote:
> > >> Some people cringe when they see a register output used as an
> > >> input clock to other synchronous logic and will go to great lengths =
to
> > >> avoid it because they might have to explain why this will never caus=
e
> > >> a timing issue. =A0
>
> > I avoid it because
> > I prefer writing code
> > to writing clock domain constraints.
>
> > > Since most DCM's aren't able to create a frequency
> > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > idea (and it will be quite precise as well).
>
> > I agree.
> > So why did you punt it?
> > A phase accumulator is portable, flexible and a precise as I need.
> > See also:http://groups.google.com/groups/search?q=3Daccum_s
>
> > =A0 =A0 =A0 =A0 -- Mike Treseler
>
> Hi Wojtek
>
> =A0 I noted with "-- Look Here ZZZ" comments where preliminary changes
> could be
> investigated to eliminate a clock domain. =A0baudTick becomes a
> synchronously delayed
> version of phaseAcc(phaseAccWidth) and can be used to detect the
> rising edge of
> phaseAcc(phaseAccWidth) after a =A0clock cycle delay. =A0I did not
> simulate it or anything.
>
> -- baud generator based on phase accumulator
> =A0 baudTickGen : process (clk) is begin
> =A0 =A0 if(rising_edge(clk))then
> =A0 =A0 =A0 phaseAcc <=3D phaseAcc + phaseAccTuning;
> =A0 =A0 =A0 baudTick <=3D phaseAcc(phaseAccWidth); =A0 =A0 =A0 =A0-- Look=
 Here ZZZ
> =A0 =A0 end if;
> =A0 end process baudTickGen;
> =A0 -- MSB of phase accumulator generates the proper baud rate
> =A0 -- Look Here ZZZ baudTick <=3D phaseAcc(phaseAccWidth);
>
> =A0 -- transmitter: 8 bits of data, no parity control, 1 stop bit
> =A0 -- Look Here ZZZ transmitter : process (baudTick) is begin
> =A0 transmitter : process (clk) is begin =A0-- Look Here
>
> =A0 =A0 -- Look HereZZZ =A0if(rising_edge(baudTick))then
> =A0 =A0 if((baudTick =3D '0') and (phaseAcc(phaseAccWidth) =3D '1')) then=
 =A0 --
> Look Here ZZZ
> =A0 =A0 =A0 =A0 showtick <=3D'1';
> =A0 =A0 =A0 if(reset =3D '1')then
> =A0 =A0 =A0 =A0 state <=3D 0;
> =A0 =A0 =A0 =A0 dataBuffer <=3D (others =3D> '0');
> =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 if(state =3D 0 and startTxD =3D '0')then
> =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '0';
> =A0 =A0 =A0 =A0 =A0 TxD <=3D '1';
> =A0 =A0 =A0 =A0 elsif(state =3D 0 and startTxD =3D '1')then
> =A0 =A0 =A0 =A0 =A0 TxD <=3D '0';
> =A0 =A0 =A0 =A0 =A0 dataBuffer <=3D dataTxD;
> =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> =A0 =A0 =A0 =A0 =A0 state <=3D state + 1;
> =A0 =A0 =A0 =A0 elsif(state > 0 and state < 9)then
> =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> =A0 =A0 =A0 =A0 =A0 TxD <=3D dataBuffer(state-1);
> =A0 =A0 =A0 =A0 =A0 state <=3D state + 1;
> =A0 =A0 =A0 =A0 elsif(state =3D 9)then
> =A0 =A0 =A0 =A0 =A0 TxD <=3D '1';
> =A0 =A0 =A0 =A0 =A0 busyTxD <=3D '1';
> =A0 =A0 =A0 =A0 =A0 state <=3D 0;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 end if;
>
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 end process;
>
> end TxD_arch;- Hide quoted text -
>
> - Show quoted text -


-- forgot  if(rising_edge(clk))then   stuff in transmitter process

On Jul 22, 9:43=A0am, Mike Treseler <mtrese...@gmail.com> wrote:
> mike wrote:
> >>>> A better design would use clk here
> >>>> and make baudTick a clock enable.
> wojtek wrote:
> >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> >>> phase accumulator works, trust me it is ok the way it is.
>
> I get the phase accumulator,
> but why bother with the fussy DCM at all?
>
> Newman wrote:
> >> Some people cringe when they see a register output used as an
> >> input clock to other synchronous logic and will go to great lengths to
> >> avoid it because they might have to explain why this will never cause
> >> a timing issue. =A0
>
> I avoid it because
> I prefer writing code
> to writing clock domain constraints.
>
> > Since most DCM's aren't able to create a frequency
> > of less than 10MHz, using phase accumulator to do it is pretty good
> > idea (and it will be quite precise as well).
>
> I agree.
> So why did you punt it?
> A phase accumulator is portable, flexible and a precise as I need.
> See also:http://groups.google.com/groups/search?q=3Daccum_s
>
> =A0 =A0 =A0 =A0 -- Mike Treseler


Hi Wojtek

  I noted with "-- Look Here ZZZ" comments where preliminary changes
could be
investigated to eliminate a clock domain.  baudTick becomes a
synchronously delayed
version of phaseAcc(phaseAccWidth) and can be used to detect the
rising edge of
phaseAcc(phaseAccWidth) after a  clock cycle delay.  I did not
simulate it or anything.

-- baud generator based on phase accumulator
  baudTickGen : process (clk) is begin
    if(rising_edge(clk))then
      phaseAcc <=3D phaseAcc + phaseAccTuning;
      baudTick <=3D phaseAcc(phaseAccWidth);        -- Look Here ZZZ
    end if;
  end process baudTickGen;
  -- MSB of phase accumulator generates the proper baud rate
  -- Look Here ZZZ baudTick <=3D phaseAcc(phaseAccWidth);


  -- transmitter: 8 bits of data, no parity control, 1 stop bit
  -- Look Here ZZZ transmitter : process (baudTick) is begin
  transmitter : process (clk) is begin  -- Look Here


    -- Look HereZZZ  if(rising_edge(baudTick))then
    if((baudTick =3D '0') and (phaseAcc(phaseAccWidth) =3D '1')) then   --
Look Here ZZZ
        showtick <=3D'1';
      if(reset =3D '1')then
        state <=3D 0;
        dataBuffer <=3D (others =3D> '0');
      else
        if(state =3D 0 and startTxD =3D '0')then
          busyTxD <=3D '0';
          TxD <=3D '1';
        elsif(state =3D 0 and startTxD =3D '1')then
          TxD <=3D '0';
          dataBuffer <=3D dataTxD;
          busyTxD <=3D '1';
          state <=3D state + 1;
        elsif(state > 0 and state < 9)then
          busyTxD <=3D '1';
          TxD <=3D dataBuffer(state-1);
          state <=3D state + 1;
        elsif(state =3D 9)then
          TxD <=3D '1';
          busyTxD <=3D '1';
          state <=3D 0;
        end if;
      end if;


         end if;
  end process;


end TxD_arch;

mike wrote:
>>>> A better design would use clk here
>>>> and make baudTick a clock enable.

wojtek wrote:
>>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
>>> phase accumulator works, trust me it is ok the way it is.

I get the phase accumulator,
but why bother with the fussy DCM at all?

Newman wrote:
>> Some people cringe when they see a register output used as an
>> input clock to other synchronous logic and will go to great lengths to
>> avoid it because they might have to explain why this will never cause
>> a timing issue.  

I avoid it because
I prefer writing code
to writing clock domain constraints.

> Since most DCM's aren't able to create a frequency
> of less than 10MHz, using phase accumulator to do it is pretty good
> idea (and it will be quite precise as well).

I agree.
So why did you punt it?
A phase accumulator is portable, flexible and a precise as I need.
See also:
http://groups.google.com/groups/search?q=accum_s

        -- Mike Treseler

On 22 Lip, 13:03, Newman <newman5...@yahoo.com> wrote:
> On Jul 22, 6:32 am, wojtek <wojtekpowiertow...@gmail.com> wrote:
>
> > >A better design would use clk here
> > >and make baudTick a clock enable.
>
> > @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > phase accumulator works, trust me it is ok the way it is.
>
> I suspect Mike knows how a phase accumulator works.  The rising edge
> of the phase accumulator can be detected without having it be a clock
> input. Some people cringe when they see a register output used as an
> input clock to other synchronous logic and will go to great lengths to
> avoid it because they might have to explain why this will never cause
> a timing issue.  In general, I would not easily discount what Mike has
> to say IMHO.

You got me wrong, I don't discount Mike's suggestions (I am very sorry
Mike if you get the impression). Just in this case, the aim of phase
accumulator is to create a clock, and using MSB of phaseAcc as clock
enable would cause the UART to work with clk frequency not with the
baudTick frequency. Since most DCM's aren't able to create a frequency
of less than 10MHz, using phase accumulator to do it is pretty good
idea (and it will be quite precise as well).