Hi,
After no response in the xilinx forums, I thought I'd post my problem
here to see if anyone has any ideas.
I have an xtclsh script that I'm using to implement a Xilinx FPGA
design using ISE. I'm having a problem determining if a synthesis
error occurred:
#########################################
# Script 1:
project open build/xilinx/$target/$target.ise
#(set device properties)
#(add files)
#(set synthesis properties)
puts "Starting Synthesis..."
if {[catch {
set result [process run "Generate Programming File"]
} msg] } {
puts "$msg"
puts "*******************************"
puts "ERROR: Synthesis failed"
puts "*******************************"
project close
exit 1
}
puts $result
project close
#########################################
The above works fine, unless an error occurs during synthesis. Below I
have introduced a deliberate error in the source. In this case, the
exception handler doesn't trigger, and $result contains "true":
#########################################
Changed current working directory to the project directory:
"C:/project/build/xilinx/target"
Starting Synthesis...
Reading design: computex_demo.prj
=========================================================================
* HDL
Compilation *
=========================================================================
Compiling verilog file "../../rtl/pads.v" in library work
ERROR:HDLCompilers:26 - "../../rtl/pads.v" line 21 Could not find
verilog include file 'pads_h.v'
Analysis of file <"demo.prj"> failed.
-->
Total memory usage is 107676 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
INFO:TclTasksC:1850 - process run : Generate Programming File is done.
true
#########################################
Any idea why this doesn't trigger the exception handler?
-----------------------------------------------------------------
A workaround is to perform the synthesis and implementation steps
explicitly.. however this runs extremely slowly for me:
#########################################
# Script 2:
project open build/xilinx/$target/$target.ise
#(set device properties)
#(add files)
#(set synthesis properties)
puts "Starting Synthesis..."
if {[catch {
process run "Synthesize - XST"
process run "Implement Design"
process run "Generate Programming File"
} msg] } {
puts "$msg"
puts "*******************************"
puts "ERROR: Synthesis failed"
puts "*******************************"
project close
exit 1
}
project close
#########################################
If there have been no source modifications, the above should do
absolutely nothing. Indeed this is the case, however it still takes
about 100 seconds to complete (Synthesise:35s, Implement:30s, Generate:
35s). Why do these steps all take so long when there is nothing to do?
Any advice would be much appreciated!