> In designer the tool SmartTimer is used for timing constraints.
> It should be no problem to constraint the delay between input and
> clock.
> Could you explain a bit more detailed what you tried and what you
> liked to get?


I'm just trying to constrain a TSU and TCO of 4ns against the clock.

If I can get the input, output and tri-state control registers into
the IOB then I presume these should be met OK, although the timing
report is including long clock delays across the device so I'm not
sure I'm specifying things against the right clock/point.


Thanks,

Nial.

On 8 Okt., 11:02, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> One other problem I've had is that the tools don't seem to be able to
> handle buried tri-state control of busses.

For internal tri-state or external?
I had no problem to control external tri-state busses with the Actel
tools. Never tried AP3, but there should be no difference.

bye Thomas

On 7 Okt., 18:58, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Does anyone have any pointers to a good document describing how to apply
> constraints to Actel FPGAs?
>
> I'm trying to transfer a design from a Cyclone II to an Actel A3P600
> (Pro-Asic 3) but am having problems applying and passing IO timing
> constraints relative to the internal clock.

In designer the tool SmartTimer is used for timing constraints.
It should be no problem to constraint the delay between input and
clock.
Could you explain a bit more detailed what you tried and what you
liked to get?

bye Thomas

> So it sounds like if you were transferring a design from Xilinx
> to Actel you'd have no problems in either case :)

No, I don't think that's the case.


> Xilinx timing constraints for I/O only work from the clock pin, not
> the internal net.  That being said you could use the datasheet
> to find timing from an internal clock net to the pad if you use
> IOB registers.

I wouldn't mind that if only I could find that information out for
the Actel device. I have an internal PLL that phase aligns the internal
clock to the input clock so need to take this into account.

It's just simple timing constraints I'm applying, it _should_ be
simple.

> Newer Xilinx parts (after Virtex and Spartan 2) don't have internal
> tristate buses.  Their synthesis emulates tristate buses with
> LUTs to ease migration of older designs, though.

I don't have any internal tri-states. I have four bi-directional
data busses, the external tri-state for these was done in the VHDL
module so I didn't have to repeat this at the top level of the
design. The Actel tools don't look like they can handle this.

> The last time I looked at Actel, my local FAE was so eager
> to grab sockets away from Xilinx he offered to port the
> design himself.  Perhaps you can get direct assistance on
> this from your FAE?

He's trying but struggling.


Nial.

On Oct 8, 5:02=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> One other problem I've had is that the tools don't seem to be able to
> handle buried tri-state control of busses.
>
> :-(
>
> Nial

So it sounds like if you were transferring a design from Xilinx
to Actel you'd have no problems in either case :)

Xilinx timing constraints for I/O only work from the clock pin, not
the internal net.  That being said you could use the datasheet
to find timing from an internal clock net to the pad if you use
IOB registers.

Newer Xilinx parts (after Virtex and Spartan 2) don't have internal
tristate buses.  Their synthesis emulates tristate buses with
LUTs to ease migration of older designs, though.

The last time I looked at Actel, my local FAE was so eager
to grab sockets away from Xilinx he offered to port the
design himself.  Perhaps you can get direct assistance on
this from your FAE?

Good Luck,
Gabor

One other problem I've had is that the tools don't seem to be able to
handle buried tri-state control of busses.

:-(


Nial 

Does anyone have any pointers to a good document describing how to apply
constraints to Actel FPGAs?

I'm trying to transfer a design from a Cyclone II to an Actel A3P600
(Pro-Asic 3) but am having problems applying and passing IO timing
constraints relative to the internal clock.

Thanks for any pointers,


Nial