Hi,
I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2
sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its MIG
controller, i installed mig v1.72 , and generated a ddr2 sdram
controller, with data width 32, with its provided test bench.
when i simulated the design with modelsim 6.1e, there were compiler
errors that showed
" data_dq runs out of its bounds", when i checked, there was these
error in its test bench after generation,
1. ddr2.v ( bus functional model) takes data width data_dq[31:0],
in its one instance, but in instantiation it was only given 8 bit data
width in all its nine instances.
2. memory_interface_top.v takes [64:0] data width, but during its
instantiation in the test bench, it was given 32 bit data width.
Please do help me in this regard