On 3 Lis, 15:18, jhal...@TheWorld.com (Joseph H Allen) wrote:
> In article <d7f10746-01b5-42bc-b472-7950aaa74...@b31g2000prf.googlegroups=
.com>,
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>
>
>
>
>
> mikel =A0<mikel...@gmail.com> wrote:
> >Hi
> >Is there a way to increase performance of Altera functional simulation
> >models? Specifically, I am using FFT core in our project and this is
> >the bottleneck of simulation speed, which I am not surprised to see,
> >given that VHO model is hundred of thousand lines of technology mapped
> >code consisting of Altera library primitives. Using Verilog *.VO does
> >not give much improvement.
>
> >Moreover, FFT core simulation performance behaves in weird fashion -
> >until core is feed in with first block of samples sim speed is quite
> >good, then when FFT processing starts it slows down (as expected). But
> >then simulation speed does not improve in idle times between
> >processing of consecutive FFT symbols =3D> when FFT core is idle.
>
> >Regards
> >Michal
>
> Write a simple model to use in place of their model. =A0Use their model o=
nly
> for final cycle-accurate checkout. =A0I'm doing this for their altmemphy-=
#"[!a[q-1]]);}
I think that for FFT it is not that easy to write simple equivalent
model as for DDR, because it makes transformation to input signal. An
idea could be to create Verilog wrapper calling FFT function as
windows executable generated through Matlab mex compiler (Altera
megacore generates matlab bit accurate model).
Best, requiring lowest effort and most accurate is to get Modelsim
precompiled core from Altera, but I am not sure if they do that.
Once I asked them to provide generation of simulation model for their
complex multiplier megawizard core and they told me that I can create
such model from non-complex multipliers on my own. Yes, I can, I even
can create complex multiplier core this way so why bother to provide
such core at all to customers.
Michal
Reply by Joseph H Allen●November 3, 20082008-11-03
In article <d7f10746-01b5-42bc-b472-7950aaa744b2@b31g2000prf.googlegroups.com>,
mikel <mikel262@gmail.com> wrote:
>Hi
>Is there a way to increase performance of Altera functional simulation
>models? Specifically, I am using FFT core in our project and this is
>the bottleneck of simulation speed, which I am not surprised to see,
>given that VHO model is hundred of thousand lines of technology mapped
>code consisting of Altera library primitives. Using Verilog *.VO does
>not give much improvement.
>
>Moreover, FFT core simulation performance behaves in weird fashion -
>until core is feed in with first block of samples sim speed is quite
>good, then when FFT processing starts it slows down (as expected). But
>then simulation speed does not improve in idle times between
>processing of consecutive FFT symbols => when FFT core is idle.
>
>Regards
>Michal
Write a simple model to use in place of their model. Use their model only
for final cycle-accurate checkout. I'm doing this for their altmemphy-based
memory controllers.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Reply by mikel●November 3, 20082008-11-03
Hi
Is there a way to increase performance of Altera functional simulation
models? Specifically, I am using FFT core in our project and this is
the bottleneck of simulation speed, which I am not surprised to see,
given that VHO model is hundred of thousand lines of technology mapped
code consisting of Altera library primitives. Using Verilog *.VO does
not give much improvement.
Moreover, FFT core simulation performance behaves in weird fashion -
until core is feed in with first block of samples sim speed is quite
good, then when FFT processing starts it slows down (as expected). But
then simulation speed does not improve in idle times between
processing of consecutive FFT symbols => when FFT core is idle.
Regards
Michal