Greg Steinke wrote:

> Another thing to check would be the TCK on the devices in the chain.
> If one of the devices is getting double-clocked then this would foul
> up the data passing through the JTAG chain. The tricky part is that a
> double-clock on any device could cause a problem, not just on the
> EPC8.

Thanks for the info. Actually we use a TCK fanout circuit, a 
74LVTH16244. The 23 members of the JTAG chain, all Altera chips, are 
ordered in 4 groups, every group gets its own TCK and TMS line. The 
lines are source terminated by a 22ohm serial resistor. The signals on 
chip pins are clean. Despite of this we often have problems with the 
programming.

The EPC8 chips seem to draw short, but extremely high current spikes 
when programmed (apr. 7-8 Amps), and even higher when doing verification 
(10-11 Amps). There are EPC8s where we cannot do verification at all - 
but the chip gets programmed correctly. We cannot exactly measure this 
current as our PS output has 12 power strips in parallel and the Board 
gets current from the Backplane on many connector pins. The current 
values above can only be seen on the display of the PS unit front panel. 
Putting several hundred uF capacitor on the EPC8 power pins can help, 
but not always. Is this correct?

Thanks,

Janos Ero
CERN Div. EP

I have used devices with JTAG interfaces that did not work correctly
if you did not take care of TRST.  This is common.  It may or may not
apply to your problem, but if TRST is used on an IC, you do want to
take care of it.

erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c27lga$jni$1@sunnews.cern.ch>...
> William Wallace wrote:
> > TRST is often used.  
> 
> Could you explain this a bit more detailled?
> 
> TRST is an optional JTAG signal and in JTAG applications you can easily 
> get the same effect using the other signals. Or am I mistaken?
> 
> Janos Ero
> CERN Div. EP

rickman wrote:

> erojr wrote:
>> 
>> rickman wrote:
>> 
>> > TRST puts the state machine in a defined state.  Most devices also reset
>> > the state machine on power up.  In addition, if you hold the TMS line
>> > high and clock TCK it will return the state machine to the starting
>> > state after 5 clock cycles, IIRC.  Of course, depending on the
>> > implementation, the mechanism that operates the state machine can get
>> > fouled up by power glitches or other anomalies.  Then the machine may
>> > get into a state that operating the TCK line may not control the state.
>> > Then you will need a power on or a TRST type reset.  I don't know that
>> > this is common, but in theory it is possible. 
>> 
>> Thank you for the description. This is exactly that I also found. I do not
>> use the TRST pin but I have never seen a case when the JTAG State Machine
>> did not return to RESET state after 5 clocks. I use the JTAG chain for
>> regular check of the FPGA input pins, not only for programming.
>> 
>> The original question was the open TRST pin, but due to the standard
>> internal pullup - I hope this is the case in Altera FPGAs too, but this
>> was not yet confirmed by anybody - the open input must not be the reason
>> for incorrect behavior. 
> 
> I don't know about Altera, but I read that TI uses just the opposite
> convention on their chips.  They require a *pulldown* on the board and
> the JTAG emulator has to have an active pullup to assert the TRST.  I
> assume the TI TRST inputs have no pullup or down.  
> 
> Why not put a TRST pullup on the board to be safe?  10K should do the
> job and not get in the way.  

The idea is to hard ground it (0 ohms) to ensure that the part does stay in 
the operating mode (TEST-LOGIC-RESET).  TRST* is asserted low.

There have been cases observed where a part that has left the TEST-LOGIC-RESET 
state and dumped garbage into the command register (the holding register is a 
don't care) has not recovered with the 5 TCK's with TMS=1.  Two causes that I 
have seen.  One, the TCK is shared with a pin in the device that has decided 
to drive out, low, clamping the system clock to a '0'.  The other was putting 
junk into the command register which sort of took the whole system down.

-- 
rk, Just an OldEngineer
"For a successful technology, reality must take precedence over public 
relations, for nature cannot be fooled."
-- R. Feynman, Appendix F.

erojr wrote:
> 
> rickman wrote:
> 
> > TRST puts the state machine in a defined state.  Most devices also reset
> > the state machine on power up.  In addition, if you hold the TMS line
> > high and clock TCK it will return the state machine to the starting
> > state after 5 clock cycles, IIRC.  Of course, depending on the
> > implementation, the mechanism that operates the state machine can get
> > fouled up by power glitches or other anomalies.  Then the machine may
> > get into a state that operating the TCK line may not control the state.
> > Then you will need a power on or a TRST type reset.  I don't know that
> > this is common, but in theory it is possible.
> 
> Thank you for the description. This is exactly that I also found. I do not
> use the TRST pin but I have never seen a case when the JTAG State Machine
> did not return to RESET state after 5 clocks. I use the JTAG chain for
> regular check of the FPGA input pins, not only for programming.
> 
> The original question was the open TRST pin, but due to the standard
> internal pullup - I hope this is the case in Altera FPGAs too, but this
> was not yet confirmed by anybody - the open input must not be the reason
> for incorrect behavior.

I don't know about Altera, but I read that TI uses just the opposite
convention on their chips.  They require a *pulldown* on the board and
the JTAG emulator has to have an active pullup to assert the TRST.  I
assume the TI TRST inputs have no pullup or down.  

Why not put a TRST pullup on the board to be safe?  10K should do the
job and not get in the way.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c29ac5$ovb$1@sunnews.cern.ch>...
> rickman wrote:
> 
> > TRST puts the state machine in a defined state.  Most devices also reset
> > the state machine on power up.  In addition, if you hold the TMS line
> > high and clock TCK it will return the state machine to the starting
> > state after 5 clock cycles, IIRC.  Of course, depending on the
> > implementation, the mechanism that operates the state machine can get
> > fouled up by power glitches or other anomalies.  Then the machine may
> > get into a state that operating the TCK line may not control the state. 
> > Then you will need a power on or a TRST type reset.  I don't know that
> > this is common, but in theory it is possible.  
> 
> Thank you for the description. This is exactly that I also found. I do not
> use the TRST pin but I have never seen a case when the JTAG State Machine
> did not return to RESET state after 5 clocks. I use the JTAG chain for 
> regular check of the FPGA input pins, not only for programming.
> 
> The original question was the open TRST pin, but due to the standard 
> internal pullup - I hope this is the case in Altera FPGAs too, but this 
> was not yet confirmed by anybody - the open input must not be the reason 
> for incorrect behavior.
> 
> Janos Ero

Hi Janos,
Altera devices that have a TRST pin have a weak internal pull-up on
them. The literature is not very clear on this, so we'll update this.
However, not all Altera devices have TRST as it is optional. The EPC8
is one of those without TSRT. It's possible that a floating TRST on
some other non-Altera device in the chain would cause such a problem,
but I imagine that most JTAG devices would have a weak pull-up on
TRST.

Another thing to check would be the TCK on the devices in the chain.
If one of the devices is getting double-clocked then this would foul
up the data passing through the JTAG chain. The tricky part is that a
double-clock on any device could cause a problem, not just on the
EPC8.

Sincerely,
Greg Steinke
gregs@altera.com
Altera Corporation

rickman wrote:

> TRST puts the state machine in a defined state.  Most devices also reset
> the state machine on power up.  In addition, if you hold the TMS line
> high and clock TCK it will return the state machine to the starting
> state after 5 clock cycles, IIRC.  Of course, depending on the
> implementation, the mechanism that operates the state machine can get
> fouled up by power glitches or other anomalies.  Then the machine may
> get into a state that operating the TCK line may not control the state. 
> Then you will need a power on or a TRST type reset.  I don't know that
> this is common, but in theory it is possible.  

Thank you for the description. This is exactly that I also found. I do not
use the TRST pin but I have never seen a case when the JTAG State Machine
did not return to RESET state after 5 clocks. I use the JTAG chain for 
regular check of the FPGA input pins, not only for programming.

The original question was the open TRST pin, but due to the standard 
internal pullup - I hope this is the case in Altera FPGAs too, but this 
was not yet confirmed by anybody - the open input must not be the reason 
for incorrect behavior.

Janos Ero

erojr wrote:
> 
> William Wallace wrote:
> > TRST is often used.
> 
> Could you explain this a bit more detailled?
> 
> TRST is an optional JTAG signal and in JTAG applications you can easily
> get the same effect using the other signals. Or am I mistaken?

TRST puts the state machine in a defined state.  Most devices also reset
the state machine on power up.  In addition, if you hold the TMS line
high and clock TCK it will return the state machine to the starting
state after 5 clock cycles, IIRC.  Of course, depending on the
implementation, the mechanism that operates the state machine can get
fouled up by power glitches or other anomalies.  Then the machine may
get into a state that operating the TCK line may not control the state. 
Then you will need a power on or a TRST type reset.  I don't know that
this is common, but in theory it is possible.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

William Wallace wrote:
> TRST is often used.  

Could you explain this a bit more detailled?

TRST is an optional JTAG signal and in JTAG applications you can easily 
get the same effect using the other signals. Or am I mistaken?

Janos Ero
CERN Div. EP

TRST is often used.  

erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c21e5p$jnd$1@sunnews.cern.ch>...
> The JTAG Standard defines a JTAG reset pin, TRST. This pin is little 
> used. All Altera docs (Datasheets, ANs) define this pin but write 
> nothing about its usage. Therefore we did not connect it at all. But we 
> experience problems in the JTAG chain: some EPC chips (especially big 
> ones, like EPC8) almost never finish the Verification phase. I am 
> wondering if this can be due to the unconnected TRST pins?
> 
> Janos Ero
> CERN Div. EP