I got the Xilinx XAPP485 and it seemed very thorough, made the entire
task truly trivial, even took into account PCB jitter and worked out
exact clock rates. Haven't had chance to try it on hardware but will
post when I do. Geez some of those built-in Xilinx designs and IPs are
impressive!

Cheers guys,
Gints

Thanks guys I'll try check it out.

If it makes it any simpler regarding locking ranges, it is for a
single camera in a single application, so the frequency is known
(40MHz)

Will post with results,

Gints

On Nov 26, 1:39=A0am, backhus <n...@nirgends.xyz> wrote:
> Hi Gints,
> there's a xapp for LVDS serializers and deserializers that work for
> CameraLink Interfaces.
> For The UCF flie have a look into the Constraints Guide of the Xilinx
> Documentation.
> A LVDS Example Application can be downloaded from
>
> http://www.xilinx.com/products/devkits/HW-SPAR3E-DISP-DK-UNI-G.htm
>
> Look under the ressources tab. There are the files.
>
> Have a nice synthesis
> =A0 =A0Eilert
>
> reganirel...@gmail.com schrieb:
>
> > Good Morning,
>
> > I need to de-serialize a camlink LVDS stream because my FPGA doesnt
> > have enough pins to accept parallel from a DS90288 etc. and am looking
> > for a push in the right direction in where to start.
>
> > I realise i need to set the constraints file such that the pins are
> > set for LVDS input, but I have no experience with constraints files,
> > so a quick run-down or resource would be great. I think I can handle
> > the rest wrt locking the 7x clock and decoding.
>
> > Any samples or resources (particularly pertaining to how UCF files
> > work) would be great.
>
> > PS: I use Xilinx 9.2i and VHDL
>
> > Gints
>
>

I'd be very interested to hear how well this works.  I've
generally stayed away from this technique in favor of the
National DC90CR28x parts for a couple reasons.  One of
course is the simplicity.  Another is the very wide lock
range.  Also when I did use the FPGA directly, I was using
a Lattice ECP2 part which has PLL's and some very useful
clocking features that made the job easier.  Even then
I needed to create different configuration files for
different input frequency ranges, due to the narrower
lock range of the FPGA's PLL wrt the National chip.

Regards,
Gabor

Hi Gints,
there's a xapp for LVDS serializers and deserializers that work for 
CameraLink Interfaces.
For The UCF flie have a look into the Constraints Guide of the Xilinx 
Documentation.
A LVDS Example Application can be downloaded from

http://www.xilinx.com/products/devkits/HW-SPAR3E-DISP-DK-UNI-G.htm

Look under the ressources tab. There are the files.

Have a nice synthesis
   Eilert



reganireland@gmail.com schrieb:
> Good Morning,
> 
> I need to de-serialize a camlink LVDS stream because my FPGA doesnt
> have enough pins to accept parallel from a DS90288 etc. and am looking
> for a push in the right direction in where to start.
> 
> I realise i need to set the constraints file such that the pins are
> set for LVDS input, but I have no experience with constraints files,
> so a quick run-down or resource would be great. I think I can handle
> the rest wrt locking the 7x clock and decoding.
> 
> Any samples or resources (particularly pertaining to how UCF files
> work) would be great.
> 
> PS: I use Xilinx 9.2i and VHDL
> 
> Gints

Good Morning,

I need to de-serialize a camlink LVDS stream because my FPGA doesnt
have enough pins to accept parallel from a DS90288 etc. and am looking
for a push in the right direction in where to start.

I realise i need to set the constraints file such that the pins are
set for LVDS input, but I have no experience with constraints files,
so a quick run-down or resource would be great. I think I can handle
the rest wrt locking the 7x clock and decoding.

Any samples or resources (particularly pertaining to how UCF files
work) would be great.

PS: I use Xilinx 9.2i and VHDL

Gints