In article <eMx1c.19775$hK6.943@newssvr29.news.prodigy.com>,
nospam <none@nowhere.net> wrote:
>
>`define MAXIMUM2( x, y ) ( ((x)>(y)) ? (x) : (y) )
>
>But Xilinx Webpack 6.2i spits out an error message saying
>something like "`MAXIMUM2 not defined."
>
>I'm guessing Xilinx's preprocessor doesn't do macros?
>Will this be supported in the future?
It's not so much a "don't do macros" issue - I think all Verilog
implementations must do basic macros to be useful, but many don't
do arguments.
Yes, arguments are standard as of 1995, but I have seen many tools
not support them.
Reply by nospam●March 3, 20042004-03-03
I've tried to define a macro-expansion in some Verilog-RTL ...
`define MAXIMUM2( x, y ) ( ((x)>(y)) ? (x) : (y) )
...
parameter IN_WIDTH = 24;
parameter OUT_WIDTH = 32;
parameter BUS_WIDTH = `MAXIMUM2( IN_WIDTH, OUT_WIDTH );
This compiles and evalutates correctly under Modelsim 5.6,
NC-Verilog 4.0, Design Compiler 2003.06-SP1, etc.
But Xilinx Webpack 6.2i spits out an error message saying
something like "`MAXIMUM2 not defined."
...
I'm guessing Xilinx's preprocessor doesn't do macros?
Will this be supported in the future?