On Jan 27, 7:08=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48
>
> <j...@jonathanleslie.com> wrote:
> >here's the source to the fifo:
> >http://grace.evergreen.edu/dtoi/arch06w/asm/KCPSM3/VHDL/bbfifo_16x8.vhd
>
> >and I "think" this is the storage:
>
> > -- SRL16E data storage
>
> > =A0data_width_loop: for i in 0 to 7 generate
> > =A0--
> > =A0attribute INIT : string;
> > =A0attribute INIT of data_srl : label is "0000";
> > =A0--
> > =A0begin
> >so here are the quickie questions:
>
> ... my answer I think would be: this is WAY too low-level to be dealing
> with unless you really need it for performance or you are down to your
> last few LUTs...
>
> This is the assembly language of hardware.
>
> >1) what's a LUT?
>
> ... basic unit of logic - typically implements a boolean function of 4
> variables. Xilinx has a neat hack (SRL16) using one LUT as a 16-bit
> shift register.
>
> >2) what do you use the reserved words ATTRIBUTE and LABEL ?
>
> When you need to force the tools to do something very specific; usually
> but not always, a low level detail.
>
> >3) what is that GENERIC MAP thing and what does(INIT =3D> X"0000")
> >mean ?
>
> Generics are generally useful; inside an entity, treat them as constants
> and base as much of a design off them as you dare. Outside, use a
> generic map to replace them with real values to parameterise your
> design.
>
> >4) INIT is the variable name right not a reserved/library word?
>
> yes - actually the generic not the variable.>5) what about STRING?
>
> A subtype of ARRAY OF CHAR - defined in the STD library I think
>
> >6) =A0but where does data_out take on the
> > =A0value of the character to be sent? =A0
>
> Part of the SRL16 hack's internal magic.
>
> Seriously; if you can treat this "bbfifo.vhd" as a black box, go ahead
> and use it. Otherwise stick to behavioural level VHDL coding until you
> find something you really can't do that way.
>
> Life's too short. If you have to get involved at this level I agree with
> Jonathan- you're in too deep.
>
> But you know how to build a counter. I suspect you know how to use it to
> address an array and read and write its contents. Do you need to spend
> time on the innards of a FIFO?
>
> If you can keep it behavioural, and let the synthesis tool do (99% of)
> this low level detail for you, I think you have a chance.
>
> - Brian

~Seriously; if you can treat this "bbfifo.vhd" as a black box, go
ahead
~ and use it.

you're the second person today to tell me that.  That's actually a bit
of a
comfort.  So any throttling of the 16 bit buffer will have to be done
outside of
the bbfifo.vhd.  I can live with that.

Thanks.

so my buffering of scheduled messages will have to live outside the
confines of
the uart package.

Well that concludes another 14 hr day.  back again at it tomorrow.

On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48
<jon@jonathanleslie.com> wrote:

>here's the source to the fifo:
>http://grace.evergreen.edu/dtoi/arch06w/asm/KCPSM3/VHDL/bbfifo_16x8.vhd
>
>and I "think" this is the storage:
>
> -- SRL16E data storage
>
>  data_width_loop: for i in 0 to 7 generate
>  --
>  attribute INIT : string;
>  attribute INIT of data_srl : label is "0000";
>  --
>  begin

>so here are the quickie questions:

... my answer I think would be: this is WAY too low-level to be dealing
with unless you really need it for performance or you are down to your
last few LUTs...

This is the assembly language of hardware.

>1) what's a LUT?
... basic unit of logic - typically implements a boolean function of 4
variables. Xilinx has a neat hack (SRL16) using one LUT as a 16-bit
shift register.

>2) what do you use the reserved words ATTRIBUTE and LABEL ?
When you need to force the tools to do something very specific; usually
but not always, a low level detail.

>3) what is that GENERIC MAP thing and what does(INIT => X"0000")
>mean ?
Generics are generally useful; inside an entity, treat them as constants
and base as much of a design off them as you dare. Outside, use a
generic map to replace them with real values to parameterise your
design.

>4) INIT is the variable name right not a reserved/library word?
yes - actually the generic not the variable.
>5) what about STRING?
A subtype of ARRAY OF CHAR - defined in the STD library I think

>6)  but where does data_out take on the
>  value of the character to be sent?  
Part of the SRL16 hack's internal magic.

Seriously; if you can treat this "bbfifo.vhd" as a black box, go ahead
and use it. Otherwise stick to behavioural level VHDL coding until you
find something you really can't do that way. 

Life's too short. If you have to get involved at this level I agree with
Jonathan- you're in too deep. 

But you know how to build a counter. I suspect you know how to use it to
address an array and read and write its contents. Do you need to spend
time on the innards of a FIFO?

If you can keep it behavioural, and let the synthesis tool do (99% of)
this low level detail for you, I think you have a chance.

- Brian

On Jan 27, 1:07 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote:
> >I've got no choice. I have a deliverable to a customer, and
> >failure is not an option. My project worked perfectly fine on a
> >DSP running C code, but the customer has dictated that It
> >must run in a pure FPGA environment.  So now I'm on the hook
> >to get it to run on a FPGA.
>
> Advice, honestly given, from one Jonathan to another:
> Get some help.  You're in over your head, which is fine
> if you're doing it for learning's sake (that's what I
> had assumed) but not if your income stream depends on it.
> You need a contractor, or another employee.   It is
> perfectly obvious you are capable of doing this stuff
> yourself, but it's also perfectly obvious that there
> is a huge amount of stuff you don't know and don't have
> time to learn.
>
> You're in Massachusetts, right?  No shortage of good
> VHDL/FPGA contractors round there, I would think.  I
> know of at least one outstanding designer in your area,
> but he's mainly a Verilog/ASIC guy so probably would
> not be the right choice.  You probably want someone
> local, so I'm not offering :-)
>
> ********** self publicity alarm **************
> we're running a VHDL training class in MD next week;
> it would suit your needs well; but it's probably
> about three weeks later than you needed it to be.
> ********** self publicity ends  **************
>
> Sorry to be so blunt.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Oh you don't have to tell me I'm in over my head. Unfortunately
I was in over my head when the prototype for this project started 2
years ago,
but I pulled a miracle then and now its expected again.  I've tried
hiring FULL-TIME
FPGA/VHDL guys, I've been through 3 so far, that's when the boss
talked me
into doing it.  I'm actually in NJ and My company has been trying to
get a foothold
into FPGA for years, always ending in failure.  I'm determined to
break that.

On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote:

>I've got no choice. I have a deliverable to a customer, and
>failure is not an option. My project worked perfectly fine on a
>DSP running C code, but the customer has dictated that It
>must run in a pure FPGA environment.  So now I'm on the hook
>to get it to run on a FPGA.

Advice, honestly given, from one Jonathan to another:
Get some help.  You're in over your head, which is fine
if you're doing it for learning's sake (that's what I
had assumed) but not if your income stream depends on it.
You need a contractor, or another employee.   It is 
perfectly obvious you are capable of doing this stuff
yourself, but it's also perfectly obvious that there
is a huge amount of stuff you don't know and don't have
time to learn.

You're in Massachusetts, right?  No shortage of good
VHDL/FPGA contractors round there, I would think.  I 
know of at least one outstanding designer in your area,
but he's mainly a Verilog/ASIC guy so probably would
not be the right choice.  You probably want someone
local, so I'm not offering :-)

********** self publicity alarm **************
we're running a VHDL training class in MD next week;
it would suit your needs well; but it's probably 
about three weeks later than you needed it to be.
********** self publicity ends  **************

Sorry to be so blunt.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.