On Feb 6, 9:20 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

> I would *guess* that ISE has correctly identified your
> 16.67MHz signal as a clock, and has correctly put it
> on to the dedicated clock tree.  But it is a nasty
> thing that you have done there, and I would prefer
> to be rid of it.  100MHz is not outrageously fast,
> so you could clock EVERYTHING from the 100MHz clock
> and merely arrange for the UART baud rate enable to
> happen one clock cycle in 54, instead of one in 9
> as you have at present.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

16.67Mhz is generated by 1/6th of the 100MHZ.  1/9th of that is
exactly that,
1/6*/19 == 1/54 of the 1000Mhz.  If this machine can't get that right,
I'm gonna
be in a whole world of hurt.


More importantly, I ran JB_LOKI_TOP. and it works like a charm:

http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap16_jbworking01.png

and I love the formatted output model.

Now the rest of the program is disabled, right now, but that's ok, I'm
very interested in this output model.
the generic map gives me the parameter concept for allowing different
messages to be go out, and I want to
explore controlling when this entity fires, for triggered calls to
Uart messages.

I definitely owe you a dinner for this one.

sincerely

Jon

On Fri, 6 Feb 2009 05:29:44 -0800 (PST), jleslie48 wrote:

>> I didn't get an answer to my question yesterday about whether
>> the OP's 16.7MHz divided clock is correctly distributed on
>> an internal clock net - i.e., has the Xilinx software
>> correctly recognized it to be a clock."

> I took some measurements with both the simulator and
> the oscilliscope on the ASCII code coming out and the
> clock time is exactly what was expected:

There's no doubt that your clock divider correctly 
generates a 16.67MHz clock (100MHz/6).  My concern
is that you have not used an internal DCM (clock 
manager block) to do it.

Clock signals have a very special status, and very 
special needs, in an FPGA.  The device has extensive
dedicated resources carefully designed to get a clock
signal to all its registers at closely the same time,
with negligible skew between them.  If you create a
derived clock and, for some reason, it gets distributed
round the chip on general-purpose routing resources
rather than on the dedicated clock tree, then some
very bad things can happen.  And those bad things
probably won't appear in simulation, unless you do 
a full back-annotated timing sim.

I would *guess* that ISE has correctly identified your
16.67MHz signal as a clock, and has correctly put it
on to the dedicated clock tree.  But it is a nasty 
thing that you have done there, and I would prefer
to be rid of it.  100MHz is not outrageously fast,
so you could clock EVERYTHING from the 100MHz clock
and merely arrange for the UART baud rate enable to
happen one clock cycle in 54, instead of one in 9 
as you have at present.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.