On Mar 11, 1:49=A0pm, Andy Peters <goo...@latke.net> wrote:
> On Mar 10, 9:52=A0pm, newman5...@yahoo.com wrote:
>
>
>
>
>
> > On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote:
>
> > > Hello Everybody !
>
> > > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitt=
er
> > > with a Virtex 4 FX12.
>
> > > What troubles me is the movement of data words from the slow system c=
lock
> > > to the faster serializer clock (fast clock is multiples of slow clock=
).
> > > Since the clocks are phase aligned by the dcm, i don't see nescessity=
 for
> > > using an async fifo, but i fail to find a simpler solution.
>
> > > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lv=
ds
> > > word periods) and 140mhz(DDR serializer).
> > > Is there any possibility for each clock domain to mark the clock cycl=
e
> > > which is aligned with all other clocks ? If all clock domains were
> > > conscious about their aligment with the other clocks, data transfers =
could
> > > be arranged in w way that avoids metastabilities.
>
> > > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20=
mhz
> > > =3D> 7 bit cells):
>
> > > State machine running in fast clock:
>
> > > =A0state_wait_sync_0 (reset_state):
> > > =A0 when slow clock is low go to state_wait_sync_1
>
> > > =A0state_wait_sync_1:
> > > =A0 when slow clock is high go to bitcell_1
>
> > > =A0bitcell_1
> > > =A0 goto bitcell_2
> > > ..
> > > =A0bitcell_5
> > > =A0 enable_load_data_from_slow_clock
> > > =A0 goto bitcell_6
>
> > > =A0bitcell_6:
> > > =A0 goto bitcell_0
>
> > > =A0bitcell_0
> > > =A0 goto bitcell_1
>
> > > enable_load_data_from_slow_clock enables a flipflop to register data =
from
> > > slow clock at bitcell_5 to grant the signal from slowclock FF enough =
setup
> > > time to fastclock FF.
>
> > > As simple as that, BUT, i am sampling a clock in transition with a ph=
ase
> > > aligned clock (at wait_sync_*). This obviously does not work. So how =
can
> > > this be done ? I am curious, there must me a standard method...
>
> > > Thanks and best regards,
> > > Julian Grahsl.
>
> > You might want to check out XAPP855 16-Channel, DDR LVDS Interface
> > with Per-Channel Alignment. =A0It is for a Virtex-5 but many of the
> > components sited are in the Virtex 4. =A0(oserdes, oddr, FIFO16 etc.)
>
> 8:1 serializing is pretty easy. 7:1? Not so much.
>
> -a- Hide quoted text -
>
> - Show quoted text -

The original post mentioned 7 bits every 20 MHz at 140 MHz so it
sounded like SDR.  A subsequent post said DDR for an effective rate of
280 MBS so it's not clear to me what's going on.

I remembered that the app note mentioned something about a recommended
clocking scheme for V5.  It did not mention V4 but I thought it may be
a descent appnote reference.  Right, 7:1 is a little different.  It
looks like the oserdes can handle 7 bits SDR. Perhaps SDR at twice the
clock mentioned with the clock output at 140 MHz is worth thinking
about.  It looked like the oserdes can handle high speeds pretty
well.  Would need to remember to handle the output timing between the
clock and data.

>
>8:1 serializing is pretty easy. 7:1? Not so much.
>
>-a

Tell be about it :-)

FYI:

I disassembled a handheld computer and want to drive the LCD Panel which
requires this format...

To be able to use a DDR Register and to keep clock speed low, i combine
two 7bit frames into one 14bit frame which is easier to build. So in fact i
have built a 14:1 serializer but with two clock periods per frame.

julian

On Mar 10, 9:52=A0pm, newman5...@yahoo.com wrote:
> On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote:
>
>
>
> > Hello Everybody !
>
> > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter
> > with a Virtex 4 FX12.
>
> > What troubles me is the movement of data words from the slow system clo=
ck
> > to the faster serializer clock (fast clock is multiples of slow clock).
> > Since the clocks are phase aligned by the dcm, i don't see nescessity f=
or
> > using an async fifo, but i fail to find a simpler solution.
>
> > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds
> > word periods) and 140mhz(DDR serializer).
> > Is there any possibility for each clock domain to mark the clock cycle
> > which is aligned with all other clocks ? If all clock domains were
> > conscious about their aligment with the other clocks, data transfers co=
uld
> > be arranged in w way that avoids metastabilities.
>
> > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mh=
z
> > =3D> 7 bit cells):
>
> > State machine running in fast clock:
>
> > =A0state_wait_sync_0 (reset_state):
> > =A0 when slow clock is low go to state_wait_sync_1
>
> > =A0state_wait_sync_1:
> > =A0 when slow clock is high go to bitcell_1
>
> > =A0bitcell_1
> > =A0 goto bitcell_2
> > ..
> > =A0bitcell_5
> > =A0 enable_load_data_from_slow_clock
> > =A0 goto bitcell_6
>
> > =A0bitcell_6:
> > =A0 goto bitcell_0
>
> > =A0bitcell_0
> > =A0 goto bitcell_1
>
> > enable_load_data_from_slow_clock enables a flipflop to register data fr=
om
> > slow clock at bitcell_5 to grant the signal from slowclock FF enough se=
tup
> > time to fastclock FF.
>
> > As simple as that, BUT, i am sampling a clock in transition with a phas=
e
> > aligned clock (at wait_sync_*). This obviously does not work. So how ca=
n
> > this be done ? I am curious, there must me a standard method...
>
> > Thanks and best regards,
> > Julian Grahsl.
>
> You might want to check out XAPP855 16-Channel, DDR LVDS Interface
> with Per-Channel Alignment. =A0It is for a Virtex-5 but many of the
> components sited are in the Virtex 4. =A0(oserdes, oddr, FIFO16 etc.)

8:1 serializing is pretty easy. 7:1? Not so much.

-a

Thank you all very much for your constructive inputs !

Kind regards,
Julian

On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote:
> Hello Everybody !
>
> I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter
> with a Virtex 4 FX12.
>
> What troubles me is the movement of data words from the slow system clock
> to the faster serializer clock (fast clock is multiples of slow clock).
> Since the clocks are phase aligned by the dcm, i don't see nescessity for
> using an async fifo, but i fail to find a simpler solution.
>
> Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds
> word periods) and 140mhz(DDR serializer).
> Is there any possibility for each clock domain to mark the clock cycle
> which is aligned with all other clocks ? If all clock domains were
> conscious about their aligment with the other clocks, data transfers coul=
d
> be arranged in w way that avoids metastabilities.
>
> My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz
> =3D> 7 bit cells):
>
> State machine running in fast clock:
>
> =A0state_wait_sync_0 (reset_state):
> =A0 when slow clock is low go to state_wait_sync_1
>
> =A0state_wait_sync_1:
> =A0 when slow clock is high go to bitcell_1
>
> =A0bitcell_1
> =A0 goto bitcell_2
> ..
> =A0bitcell_5
> =A0 enable_load_data_from_slow_clock
> =A0 goto bitcell_6
>
> =A0bitcell_6:
> =A0 goto bitcell_0
>
> =A0bitcell_0
> =A0 goto bitcell_1
>
> enable_load_data_from_slow_clock enables a flipflop to register data from
> slow clock at bitcell_5 to grant the signal from slowclock FF enough setu=
p
> time to fastclock FF.
>
> As simple as that, BUT, i am sampling a clock in transition with a phase
> aligned clock (at wait_sync_*). This obviously does not work. So how can
> this be done ? I am curious, there must me a standard method...
>
> Thanks and best regards,
> Julian Grahsl.

You might want to check out XAPP855 16-Channel, DDR LVDS Interface
with Per-Channel Alignment.  It is for a Virtex-5 but many of the
components sited are in the Virtex 4.  (oserdes, oddr, FIFO16 etc.)

On Mar 10, 6:59=A0am, "jag9624" <ma...@grahsl.net> wrote:
> Hi Jerzy !
>
> My main problem is synchronizing two processes:
>
> 1) My LVDS clock, which runs at 40 Mhz.
> 2) The serialiser which transmits 7 bits within each 40 Mhz period.
>
> The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate is
> effectively 280Mhz)
>
> The serialiser needs to lock on the LVDS Clock to figure out where to
> place the first bit. I dont know how to accomplish this. I cant observe t=
he
> 40 Mhz clock from the 140Mhz domain without risking metastabilities...
>
> I fact i found a working solution, but i don't like it:
> I use the LOCKED signal created by the DCM (Virtex4) which gives me the
> exact point where all clocks are aligned. So synchronization is done only
> once and never checked again.

I agree with Jerzy -- use some sort of dual-port to cross the clock
domain.

I did a Camera Link serializer (DS90CR287 replacement) in a Spartan
3AN, and the only way to get it to work was to create a ping-pong
buffer from a dual-port RAM in LUTs. The write side is clocked at the
parallel data rate, and on each rising edge a new data word (28 bits)
is written to one or the other location. The read side clock is at
3.5X the parallel rate, and a little state machine reads the pong
buffer during the time the write side is updating the ping buffer (and
the converse). The 3.5X also clocks the ODDR2s and a mux which
determines which read bits drive the ODDR2 D0 and D1 input. (Hint: use
DDR_ALIGNMENT =3D "C0" so you write both D0 and D1 on the rising edge of
the clock.)

Oh, yeah, there's a Xilinx app note about doing a 7:1 serializer, but
it's typically awful.

-a

On Tue, 10 Mar 2009 08:59:47 -0500
"jag9624" <mail2@grahsl.net> wrote:

> Hi Jerzy !
> 
> My main problem is synchronizing two processes:
> 
> 1) My LVDS clock, which runs at 40 Mhz. 
> 2) The serialiser which transmits 7 bits within each 40 Mhz period.
> 
> The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate
> is effectively 280Mhz)
> 
> The serialiser needs to lock on the LVDS Clock to figure out where to
> place the first bit. I dont know how to accomplish this. I cant
> observe the 40 Mhz clock from the 140Mhz domain without risking
> metastabilities...
> 
> I fact i found a working solution, but i don't like it:
> I use the LOCKED signal created by the DCM (Virtex4) which gives me
> the exact point where all clocks are aligned. So synchronization is
> done only once and never checked again.
> 
> regards,
> Julian

The DCM is, if I recall correctly, keeping all of your clocks rising
edge aligned, i.e. every 50 ns you have a rising 140 MHz edge happening
at (nearly) the same time as a 40 MHz rising edge, and 25 ns after
that, you'll always have your next rising edge on the 40 MHz coincident
with the falling edge of the 140 MHz clock.

If you set a flip-flop to toggle on every tick of the 40 MHz clock,
then sample that output with both rising and falling 140 MHz flop, you
should be able to resolve the phase relationship unambiguously without
any metastability risk.  Not because it's a general solution, but
specifically because you've got the DCM enforcing a known phase
relationship.

Really, all that is just a special case of the classic
pulse-toggle-pulse synchronizer.  You can just get away without the
extra resynchronizer stages on the second side because of the known
phases.  Likewise, because of that, there's a way to force the static
timing analysis to look at those paths if you need some verification,
but what the exact syntax on that is I can't recall and I haven't had
enough coffee yet to brave the depths of CGD.PDF again.


-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Hi Jerzy !

My main problem is synchronizing two processes:

1) My LVDS clock, which runs at 40 Mhz. 
2) The serialiser which transmits 7 bits within each 40 Mhz period.

The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate is
effectively 280Mhz)

The serialiser needs to lock on the LVDS Clock to figure out where to
place the first bit. I dont know how to accomplish this. I cant observe the
40 Mhz clock from the 140Mhz domain without risking metastabilities...

I fact i found a working solution, but i don't like it:
I use the LOCKED signal created by the DCM (Virtex4) which gives me the
exact point where all clocks are aligned. So synchronization is done only
once and never checked again.

regards,
Julian

On 10 Mar, 12:48, "jag9624" <ma...@grahsl.net> wrote:
> Hello Everybody !
>
> I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter
> with a Virtex 4 FX12.
>
> What troubles me is the movement of data words from the slow system clock
> to the faster serializer clock (fast clock is multiples of slow clock).
> Since the clocks are phase aligned by the dcm, i don't see nescessity for
> using an async fifo, but i fail to find a simpler solution.
>
> Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds
> word periods) and 140mhz(DDR serializer).
> Is there any possibility for each clock domain to mark the clock cycle
> which is aligned with all other clocks ? If all clock domains were
> conscious about their aligment with the other clocks, data transfers coul=
d
> be arranged in w way that avoids metastabilities.
>
> My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz
> =3D> 7 bit cells):
>
> State machine running in fast clock:
>
> =A0state_wait_sync_0 (reset_state):
> =A0 when slow clock is low go to state_wait_sync_1
>
> =A0state_wait_sync_1:
> =A0 when slow clock is high go to bitcell_1
>
> =A0bitcell_1
> =A0 goto bitcell_2
> ..
> =A0bitcell_5
> =A0 enable_load_data_from_slow_clock
> =A0 goto bitcell_6
>
> =A0bitcell_6:
> =A0 goto bitcell_0
>
> =A0bitcell_0
> =A0 goto bitcell_1
>
> enable_load_data_from_slow_clock enables a flipflop to register data from
> slow clock at bitcell_5 to grant the signal from slowclock FF enough setu=
p
> time to fastclock FF.
>
> As simple as that, BUT, i am sampling a clock in transition with a phase
> aligned clock (at wait_sync_*). This obviously does not work. So how can
> this be done ? I am curious, there must me a standard method...
>
> Thanks and best regards,
> Julian Grahsl.

Mhm... I don't prefer this kind of solution. What can I advice you is
you use block RAM for repacking data, or use 140MHz clock with
CLOCK_ENABLE. Then you be sure, that everything will work well.

Kind Regards,
Jerzy Gbur

Hello Everybody !

I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter
with a Virtex 4 FX12.

What troubles me is the movement of data words from the slow system clock
to the faster serializer clock (fast clock is multiples of slow clock).
Since the clocks are phase aligned by the dcm, i don't see nescessity for
using an async fifo, but i fail to find a simpler solution.

Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds
word periods) and 140mhz(DDR serializer).
Is there any possibility for each clock domain to mark the clock cycle
which is aligned with all other clocks ? If all clock domains were
conscious about their aligment with the other clocks, data transfers could
be arranged in w way that avoids metastabilities.

My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz
=> 7 bit cells):

State machine running in fast clock:

 state_wait_sync_0 (reset_state):
  when slow clock is low go to state_wait_sync_1

 state_wait_sync_1:
  when slow clock is high go to bitcell_1

 bitcell_1
  goto bitcell_2
..
 bitcell_5
  enable_load_data_from_slow_clock
  goto bitcell_6

 bitcell_6:
  goto bitcell_0

 bitcell_0
  goto bitcell_1

enable_load_data_from_slow_clock enables a flipflop to register data from
slow clock at bitcell_5 to grant the signal from slowclock FF enough setup
time to fastclock FF.

As simple as that, BUT, i am sampling a clock in transition with a phase
aligned clock (at wait_sync_*). This obviously does not work. So how can
this be done ? I am curious, there must me a standard method...

Thanks and best regards,
Julian Grahsl.