On May 13, 1:54=A0pm, ligu...@gmail.com wrote:
> Dear All:
>
> I am thinking about my system, the picture is here:
>
> http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
>
> I want to transfer the raw/processed image sensor data to USB 2.0 or
> dpram.
>
> Two choices:
>
> 1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-
>
> >DPRAM
>
> 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
> EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
> DSP works as a coprocessor.
> In choice 2, the USB could also connect from DSP but this will
> accelerate processed data transfer, decelerate the raw data transfer.
>
> Other questions:
>
> I also need to store raw data, thus the data saving path will be
> different:
> Choice 1: the raw data will be from ADC -> DSP -> FLASH
> Choice 2: the raw data will be from ADC -> FLASH -> DSP
=20
~~~~FPGA->FLASH
> It will meet the same question when I save processed data on board.
>
> The last question is FIFO vs. DPRAM, FIFO could be implemented in
> FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
> flexibility for sure.
>
> Thanks!

Dear All:

I am thinking about my system, the picture is here:

http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/

I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.

Two choices:

1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-
>DPRAM

2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
DSP works as a coprocessor.
In choice 2, the USB could also connect from DSP but this will
accelerate processed data transfer, decelerate the raw data transfer.

Other questions:

I also need to store raw data, thus the data saving path will be
different:
Choice 1: the raw data will be from ADC -> DSP -> FLASH
Choice 2: the raw data will be from ADC -> FLASH -> DSP
It will meet the same question when I save processed data on board.

The last question is FIFO vs. DPRAM, FIFO could be implemented in
FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
flexibility for sure.

Thanks!