> I disagree. I think toroidal is the optimum topology.
Torodial is/was already done (if I remember right it was no FPGA, but one of
Raytheone many core/massiv parallel units).
Its relativly easy doable. You could also do it with a island style FPGA
with slightly different routing, by interleaving:
------- ----- -----
| \/ \/ \
x---x x x x x x--x
| /\ /\ |
------- ---- ------
(I am no good ASCI artist, but I hope the idea is clear (x island, rest
routing, same approach for vertical, as this is only horizontaly))
Florian
Reply by Symon●May 27, 20092009-05-27
halong wrote:
>
> Spherical would be ideal
I disagree. I think toroidal is the optimum topology.
Syms.
Reply by rickman●May 27, 20092009-05-27
On May 26, 1:10=A0pm, halong <cco...@netscape.net> wrote:
> On May 26, 11:00=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
> > On May 25, 12:47=A0am, yuchi...@gmail.com wrote:
>
> > Hexagon is possible, but it would generate more trouble for bus
> > interconnections and it would generate waste materials along chip
> > boundaries.
>
> > For more information, Xilinx patent: 7274214, "Efficient tile layout
> > for a programmable logic device.pdf"http://www.google.com/patents?id=3D=
dGeEAAAAEBAJ&dq=3Dpatent:7274214&as_dr...
>
> > I have carefully and thoroughly read the patent, but with purposes
> > different from yours. It is very interesting and instructive.
>
> > Weng- Hide quoted text -
>
> > - Show quoted text -
>
> Spherical would be ideal
You mean like Ball Semiconductor tried?
Rick
Reply by halong●May 26, 20092009-05-26
On May 26, 11:00=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On May 25, 12:47=A0am, yuchi...@gmail.com wrote:
>
>
>
>
>
>
> Hexagon is possible, but it would generate more trouble for bus
> interconnections and it would generate waste materials along chip
> boundaries.
>
> For more information, Xilinx patent: 7274214, "Efficient tile layout
> for a programmable logic device.pdf"http://www.google.com/patents?id=3DdG=
eEAAAAEBAJ&dq=3Dpatent:7274214&as_dr...
>
> I have carefully and thoroughly read the patent, but with purposes
> different from yours. It is very interesting and instructive.
>
> Weng- Hide quoted text -
>
> - Show quoted text -
Spherical would be ideal
Reply by Weng Tianxiang●May 26, 20092009-05-26
On May 25, 12:47=A0am, yuchi...@gmail.com wrote:
> Dear all,
> I am very interested in the arcchitecture of FPGA of commercial
> product. But I have the following questions:
> 1. Is that all logic elements in FPGA are rectangular in shape (e.g.
> CLB) and why ?
> 2. Why DSP/ Memory are arranged in column rather than putting
> together?
> 3. Why DSP and Memory are rectangular in shape ?
> 4. Are there special wire connection between DSP or memory ? e.g. bus
> base connection.
>
> Can expert answer my questions ?
>
> Thank you very much for your help.
>
> Best regards,
> Yu
Hi Yu,
The answer doesn't seem to be as simple as people thinks: I have more
than once asked myself if there is a better tile shape, but its final
decision is based on manufacure experiences, not on guess work.
One block is called one tile in the FPGA architecture.
FPGA manufacturers usually duplicate many tiles to create a lot
versions of products of different sizes. That generates a problem you
have asked: what is the best shape one tile should have to make
manufacture as simple as possible while keeping no holes among them to
maximum the number of products within a fixed one silicon chip?
Hexagon is possible, but it would generate more trouble for bus
interconnections and it would generate waste materials along chip
boundaries.
For more information, Xilinx patent: 7274214, "Efficient tile layout
for a programmable logic device.pdf"
http://www.google.com/patents?id=3DdGeEAAAAEBAJ&dq=3Dpatent:7274214&as_drrb=
_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_drrb_i=
s=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D
I have carefully and thoroughly read the patent, but with purposes
different from yours. It is very interesting and instructive.
Weng
Reply by Nobby Anderson●May 26, 20092009-05-26
MM <mbmsv@yahoo.com> wrote:
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:gvf2nc$r78$1@news.eternal-september.org...
>> MM wrote:
>>>> 3. Why DSP and Memory are rectangular in shape ?
>>>
>>> Do you mean why they are not round?
>>>
>>>
>> No, why are they rectangular? Do you know?
>
> Poincare�s conjecture says that no matter what it looks like, it's
> a sphere.
That's a load of balls!
Reply by MM●May 26, 20092009-05-26
"Symon" <symon_brewer@hotmail.com> wrote in message
news:gvf2nc$r78$1@news.eternal-september.org...
> MM wrote:
>>> 3. Why DSP and Memory are rectangular in shape ?
>>
>> Do you mean why they are not round?
>>
>>
> No, why are they rectangular? Do you know?
Poincare�s conjecture says that no matter what it looks like, it�s a sphere.
Reply by Nobby Anderson●May 25, 20092009-05-25
Symon <symon_brewer@hotmail.com> wrote:
> MM wrote:
>>> 3. Why DSP and Memory are rectangular in shape ?
>>
>> Do you mean why they are not round?
>>
>>
> No, why are they rectangular? Do you know? The person who set the assignment
> does.
>
There you go, they actually don't. That's why they're asking the
question. Then they have a whole classload of students to try and
find the answer for then. Thankfully some of them are smart enough to
come and ask here rather than doing their own homework assignments.
Nobby
Reply by Symon●May 25, 20092009-05-25
MM wrote:
>> 3. Why DSP and Memory are rectangular in shape ?
>
> Do you mean why they are not round?
>
>
No, why are they rectangular? Do you know? The person who set the assignment
does.
Reply by MM●May 25, 20092009-05-25
> 3. Why DSP and Memory are rectangular in shape ?