Reply by Antt...@googlemail.com●September 11, 20092009-09-11
On Sep 11, 5:38=A0pm, nobody <cydrollin...@gmail.com> wrote:
> On Sep 11, 12:17=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > > Completion,
>
> > > The FPGA never releases =A0the Global Three State(GTS) after done goe=
s
> > > high, described in DS312 pg. 107, because the fpga_cclk shuts down on=
e
> > > clock cycle to early. After the revision of taking out the need to
> > > program while FPGA_initb is high gives the extra fpga_cclk needed to
> > > release GTS signal and drives the High Z FPGA_d bus. One stinking
> > > clock cycle who knew?
>
> > > Sincerely,
>
> > > Cy Drollinger
>
> > Cy
>
> > this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
> > working
> > (this is not same as done=3D1)
>
> > it is always wise to send extra clocks after done=3D1... this is for me
> > common knowledge
> > i should have suggested this earlier, but i assumed you DID know that
> > FPGA was
> > actually driving the pins
>
> > btw bus conflict and non-driving bus can be seen as different with DSO
> > or even multimeter
>
> > Antti
>
> Antti,
>
> Do not beat yourself up about the OBVIOUS, you had a good suggestion
> about the High "Z" bus and my problem when you asked me to isolate
> this =A0feature on unused pins. I got more familiar with High Z
> circuitry and its behavior, BTW Because it is written in Synthesis and
> in a constraints file does not make it so, Synthesis can override
> these as in defaults and preferences set within Synthesis.
>
> Cy
you can not change the io type with constraints.. only by RTL
you can change settings for unused pins with some settings
but the in/out/bidir is dictated by RTL code
Antti
Reply by nobody●September 11, 20092009-09-11
On Sep 11, 12:17=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > Completion,
>
> > The FPGA never releases =A0the Global Three State(GTS) after done goes
> > high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> > clock cycle to early. After the revision of taking out the need to
> > program while FPGA_initb is high gives the extra fpga_cclk needed to
> > release GTS signal and drives the High Z FPGA_d bus. One stinking
> > clock cycle who knew?
>
> > Sincerely,
>
> > Cy Drollinger
>
> Cy
>
> this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
> working
> (this is not same as done=3D1)
>
> it is always wise to send extra clocks after done=3D1... this is for me
> common knowledge
> i should have suggested this earlier, but i assumed you DID know that
> FPGA was
> actually driving the pins
>
> btw bus conflict and non-driving bus can be seen as different with DSO
> or even multimeter
>
> Antti
Antti,
Do not beat yourself up about the OBVIOUS, you had a good suggestion
about the High "Z" bus and my problem when you asked me to isolate
this feature on unused pins. I got more familiar with High Z
circuitry and its behavior, BTW Because it is written in Synthesis and
in a constraints file does not make it so, Synthesis can override
these as in defaults and preferences set within Synthesis.
Cy
Reply by Antt...@googlemail.com●September 11, 20092009-09-11
On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Completion,
>
> The FPGA never releases =A0the Global Three State(GTS) after done goes
> high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> clock cycle to early. After the revision of taking out the need to
> program while FPGA_initb is high gives the extra fpga_cclk needed to
> release GTS signal and drives the High Z FPGA_d bus. One stinking
> clock cycle who knew?
>
> Sincerely,
>
> Cy Drollinger
Cy
this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
working
(this is not same as done=3D1)
it is always wise to send extra clocks after done=3D1... this is for me
common knowledge
i should have suggested this earlier, but i assumed you DID know that
FPGA was
actually driving the pins
btw bus conflict and non-driving bus can be seen as different with DSO
or even multimeter
Antti
Reply by gabor●September 10, 20092009-09-10
On Sep 10, 4:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Completion,
>
> The FPGA never releases =A0the Global Three State(GTS) after done goes
> high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> clock cycle to early. After the revision of taking out the need to
> program while FPGA_initb is high gives the extra fpga_cclk needed to
> release GTS signal and drives the High Z FPGA_d bus. One stinking
> clock cycle who knew?
>
> Sincerely,
>
> Cy Drollinger
You can change the order of the startup events in the bitgen
options. I've have similar problems when using a micro to
load the FPGA and stopping as soon as DONE is high. The
default startup sequence sets DONE high before releasing
GSR. For a design with only one FPGA this is not necessary.
The intent is to synchronize startup of multiple devices
in a chain.
Regards,
Gabor
Reply by nobody●September 10, 20092009-09-10
Completion,
The FPGA never releases the Global Three State(GTS) after done goes
high, described in DS312 pg. 107, because the fpga_cclk shuts down one
clock cycle to early. After the revision of taking out the need to
program while FPGA_initb is high gives the extra fpga_cclk needed to
release GTS signal and drives the High Z FPGA_d bus. One stinking
clock cycle who knew?
Sincerely,
Cy Drollinger
Reply by Antt...@googlemail.com●September 10, 20092009-09-10
On Sep 10, 1:18=A0am, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> Do not want to raise any hackles, but you are correct about the
> demandperipherials knock off, perceptive. I talked with Bob Smith
> about a couple of things and he basically said go away, I understand
> and with no further ado I did. Here is a picture of my finished
> product,http://www.mediafire.com/?sharekey=3D923066edf8d516eeed24a2875c7f=
a58ee0...
>
> I agree about the so simple part, However there is something
> interesting in this problem I have described, I just have not found
> it.
>
> SPI works fine and is not part of the usb programming, indirect JTAG
> only.
>
> I am not sure how the FT245RL can strobe its own read line and produce
> a CCLK in order to load the data into FPGA, if you are willing to
> elaborate im willing to read.
>
> I went for a swim to clear my head it works every time.
>
> Will give your suggestions a closer look.
>
> I have so much completed on this board from absolutely nothing to 95%
> working it is a great project and will be taking this open source. I
> wonder why my work is not necessary?
>
> Antti, thanks for chatting not looking to raise any hackles, but am
> glad for the help.
>
> Cy Drollinger
Cy
pretty much NO ONE in the open-source community is inteterested in 4
layer PCB with S3E
ALL S3E board level products are DISCONTINUED by Xilinx
if Xilinx has discontinued, why do you want to promote something
Xilinx itself wants to forget?
your board is TOO expensive
option:
step 1:
take S3AN add LDO, and RJ45 jack and 100 mil header
PCB should be REAL simple and 2 layers only
step 2:
ask U2TOOL OEM pricing (coming soon www.u2tool.com )
step 3:
bundle items [1] and [2]
you can do step 2 before step 1 :)
Antti
Reply by nobody●September 9, 20092009-09-09
Antti,
Do not want to raise any hackles, but you are correct about the
demandperipherials knock off, perceptive. I talked with Bob Smith
about a couple of things and he basically said go away, I understand
and with no further ado I did. Here is a picture of my finished
product, http://www.mediafire.com/?sharekey=923066edf8d516eeed24a2875c7fa58ee04e75f6e8ebb871
I agree about the so simple part, However there is something
interesting in this problem I have described, I just have not found
it.
SPI works fine and is not part of the usb programming, indirect JTAG
only.
I am not sure how the FT245RL can strobe its own read line and produce
a CCLK in order to load the data into FPGA, if you are willing to
elaborate im willing to read.
I went for a swim to clear my head it works every time.
Will give your suggestions a closer look.
I have so much completed on this board from absolutely nothing to 95%
working it is a great project and will be taking this open source. I
wonder why my work is not necessary?
Antti, thanks for chatting not looking to raise any hackles, but am
glad for the help.
Cy Drollinger
Reply by Antt...@googlemail.com●September 9, 20092009-09-09
On Sep 8, 4:34=A0am, nobody <cydrollin...@gmail.com> wrote:
> After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
> an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
> data and fpga_cclk into the FPGA the done pin goes high. The problem I
> am having is the bidirectional does not release and allow the FPGA to
> drive the data bus to CPLD and then finally into an external 8 LED
> bank. I am fairly confident that the FPGA is loaded correctly with the
> bin file, by accident I reprogrammed the CPLD releasing the bus the
> FPGA, having been programmed, drove the bidirectional data bus and the
> lit the 8 LED bank appropriately. Any help on this issues would be
> apprciated, thank you. CODE:
>
> -------------------------------------------------------------------------=
BTW why are you doing something like this?
to clone that
http://www.demandperipherals.com/
there is no reason todo that IMHO
Antti
PS there is no reason to connect data bus to the CPLD :)
the SPI flash can be programmed without that too..
so just DISCONNECT the data bus from the cpld
connect FT245 to FPGA directly
Reply by Antt...@googlemail.com●September 9, 20092009-09-09
On Sep 9, 8:37=A0pm, nobody <cydrollin...@gmail.com> wrote:
> On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > > <antti.luk...@googlemail.com> wrote:
> > > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > > Antti
>
> > > > > Thanks Antti,
>
> > > > > Ive tried that.
>
> > > > > Cy drollinger
>
> > > > and? problem solved or not?
>
> > > > Antti
>
> > > Antti,
>
> > > No, That has the same effect as the current VDHL Bidirectional bus
> > > attempt. The FPGA is being programmed but the bus does not release. I=
t
> > > releases when the CPLD is reprogrammed via JTAG, this is not an
> > > option. I am not to familiar with driving a common trace between two
> > > programmable chips and maybe missing something conceptually. I have
> > > been just reading examples of bidirectional buses and have used a
> > > couple different solutions, which are quite similar. All have the sam=
e
> > > effect not releasing after the slave parallel programming of the FPGA
> > > is complete. I might not be explaining the problem thoroughly. Well,
> > > back at it. I will let you know when I get the problem solved.
>
> > > Cy Drollinger
>
> > connect done to JUMPER
> > bus to free IO
> > test
>
> > the code works, so if you dont see bus released problem is somewhere
> > else
>
> > Antti
>
> Antti,
>
> What about the synthesis tool not actually handling the the VHDL
> statement:
>
> the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;
>
> in the appropriate way. I asked a question about setting a pullup on a
> few of the Switch pins of the CPLD and I learned that using a pullup
> on one of the pin in the XC2C64A causes all pins to in a pullup state.
> After talking with another individual their maybe some primitives that
> need to be instantiated in order for the the high Z bus to be
> implemented?
> I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
> 100 ns, I know the FPGA can drive the LEDs through the CPLD and the
> pins that programmed the FPGA, but not immediately after the CPLD
> programs the FPGA. The CPLD must be reprogrammed through the JTAG
> leading me to believe there is something wrong with the above VHDL
> statement either in timing, something hangs, or the synthesis tool is
> not performing what I think I am asking it to do, Go to a high Z state
> after the FPGA is programmed.
>
> Antti, Thank you for taking time to give solutions and time thinking
> about my problem, it is appreciated.
>
> Cy Drollinger
the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;
this WILL RELEASE the pins.
even Xilinx tools cant be that bad to fail on this.
if this is what you have, and FPGA_done IS 1
then bus is tristated as well
if not take a break.
it helps
if you think the synthesis tools fail, DO AS I TOLD YOU
make the "Z" on spare pins of the CPLD and check with multimeter and
finger
what you are doing is SO simple.. its hard todo it wrong...
Antti
Reply by nobody●September 9, 20092009-09-09
On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
>
>
> > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > <antti.luk...@googlemail.com> wrote:
> > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > Antti
>
> > > > Thanks Antti,
>
> > > > Ive tried that.
>
> > > > Cy drollinger
>
> > > and? problem solved or not?
>
> > > Antti
>
> > Antti,
>
> > No, That has the same effect as the current VDHL Bidirectional bus
> > attempt. The FPGA is being programmed but the bus does not release. It
> > releases when the CPLD is reprogrammed via JTAG, this is not an
> > option. I am not to familiar with driving a common trace between two
> > programmable chips and maybe missing something conceptually. I have
> > been just reading examples of bidirectional buses and have used a
> > couple different solutions, which are quite similar. All have the same
> > effect not releasing after the slave parallel programming of the FPGA
> > is complete. I might not be explaining the problem thoroughly. Well,
> > back at it. I will let you know when I get the problem solved.
>
> > Cy Drollinger
>
> connect done to JUMPER
> bus to free IO
> test
>
> the code works, so if you dont see bus released problem is somewhere
> else
>
> Antti
Antti,
What about the synthesis tool not actually handling the the VHDL
statement:
the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;
in the appropriate way. I asked a question about setting a pullup on a
few of the Switch pins of the CPLD and I learned that using a pullup
on one of the pin in the XC2C64A causes all pins to in a pullup state.
After talking with another individual their maybe some primitives that
need to be instantiated in order for the the high Z bus to be
implemented?
I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
100 ns, I know the FPGA can drive the LEDs through the CPLD and the
pins that programmed the FPGA, but not immediately after the CPLD
programs the FPGA. The CPLD must be reprogrammed through the JTAG
leading me to believe there is something wrong with the above VHDL
statement either in timing, something hangs, or the synthesis tool is
not performing what I think I am asking it to do, Go to a high Z state
after the FPGA is programmed.
Antti, Thank you for taking time to give solutions and time thinking
about my problem, it is appreciated.
Cy Drollinger