An eight bit bus on the PCB is used for both programming an FPGA,
XC3S250EVQ100, as a slave parallel configuration from a CPLD,
XC2C64AVQ100, and secondarily carry information back to the CPLD after
programming. This programming configuration releases the done pin,
however unable to drive an external set of LEDs from the bus,
mentioned above. Code is published in a message" Bidirectional Bus"
9/7/09. I am wondering about driving the pins, CPLD, into a high "Z"
state and therefore unable to read from them as well. I would
appreciate some insight into driving this bus as a programmer and then
as a data out from the FPGA.

Thankyou

Cy Drollinger